mch@computing-maths.cardiff.ac.uk (Major Kano) (05/20/88)
Thanks to everyone on the net who posted, and to the three people who sent e-maile. It seems clear that the 80960 WAS, after all, the Intel RISC CPU that was referred to in the magazine article I read. Many people were amused or critical of my remark about a "real" CPU. I had expected that people who are somewhat older than me and with many more years of experience of computer architectures in general might be able to infer from the inverted commas (= semi-humourous in the English language) the correct meaning, but as it seems that I must have been a touch obtuse, let me spell it out: By a "real" (the inverted ''s should have given you all a clue) I meant a CPU that was * intended and optimised * for PC's and workstations (a la SUN, etc), and to run UNIX (tm AT&T) or something like that, rather than one intended for process control. It seemed to me at the time that a Motorola 88000 counterpart (as the 80386 could be said to be a 68020 counterpart) was what the magazine article was referring to. I should point out that one respondent thought that putting the '960 in a workstation would actually be quite feasible/desirable. OK, from what I know of the '960, that may well be so, but I can't say for certain as I know zilch about it's memory model. As for the 80486, S. McGready had this to say: >Apropos the 486, what we are allowed to say is: > > 1) it will be compatible with the 386; > 2) it will be faster than the 386; > 3) it will be available in the future; > >You will hear claims that the 486 uses "RISC design techniques" to reduce >the number of clocks per instruction. Do not misinterpret this as a statement >that the *86 family is suddenly a RISC architecture. I rather think most people will assume this to mean a 68030/C100 rip-off (:-) that is, Harvard inside with RISC core, JVN outside, amongst other things. (Rather what I'd sort-of hoped the '386 to be when I first knew about it, in late 1985.) > >I suggest that you contact your nearest Intel Sales Office >(Intel UK, Pipers Way, Swindown, Wiltshire SN3 1RJ; (0793) 69 60 00) >for more information. > >S. McGeady >Intel Corp. I had thought of contacting the Pipers Way office, but I didn't think any '486 info would have been available yet from Intel (apart from the foregoing). I probably will in the semi-near future. Thanks again to everyone who mailed or posted. Regards, -- Martin C. Howe, University College Cardiff | "You actually program in 'C' mch@vax1.computing-maths.cardiff.ac.uk. | WITHOUT regular eye-tests ?!" -------------------------------------------+-----+------------------------------ My cats know more about UCC's opinions than I do.| MOSH! In the name of ANTHRAX!
mash@mips.COM (John Mashey) (05/29/88)
In article <411@cf-cm.UUCP> mch@computing-maths.cardiff.ac.uk (Major Kano) writes: ... > As for the 80486, S. McGready had this to say: >>You will hear claims that the 486 uses "RISC design techniques" to reduce >>the number of clocks per instruction. Do not misinterpret this as a statement >>that the *86 family is suddenly a RISC architecture. > I rather think most people will assume this to mean a 68030/C100 rip-off (:-) >that is, Harvard inside with RISC core, JVN outside, amongst other things. >(Rather what I'd sort-of hoped the '386 to be when I first knew about it, in >late 1985.) I'm not sure where the "rip-off" part comes from. Making CISC architectures go faster by making them more RISClike on the inside has a long tradition amongst mainframes and superminis. It is not surprising that similar techniques would be used with CISC micros as the necessary silicon becomes available. Given everything else a 386 needs to do, it doesn't seem like there was enough silicon in that technology round to do the other things that were hoped-for. -- -john mashey DISCLAIMER: <generic disclaimer, I speak for me only, etc> UUCP: {ames,decwrl,prls,pyramid}!mips!mash OR mash@mips.com DDD: 408-991-0253 or 408-720-1700, x253 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086