kahn@batcomputer.tn.cornell.edu (Shahin Kahn) (09/15/90)
The latest issue of Supercomputer Review has a little report on a company working a "Minimum" instruction-set computer. What is this? Very fast boolean algebra? Shahin.
crowl@cs.rochester.edu (Lawrence Crowl) (09/15/90)
In article <1990Sep14.173018.10197@batcomputer.tn.cornell.edu> kahn@batcomputer.tn.cornell.edu (Shahin Kahn) writes: >The latest issue of Supercomputer Review has a little report on a company >working a "Minimum" instruction-set computer. What is this? Very fast >boolean algebra? I do not know what that project is, but I once played with an instruction set with two instructions: "increment" and "decrement and branch conditionally". Moving a number from one storage location to another took a loop. Multiplying two numbers took three nested loops. (Exercise for the reader: Why is "decrement and branch if not zero" better than "decrement and branch if zero"?) It was entertaining, but that's about it. I'm willing to wager that the "Minimum" above has some measure of practical in it. You can also have a single instruction "subtract and branch conditionally". It has the advantage of not requring an opcode in the instruction, just a couple of addresses. Which instruction set is minimal depends on whether you count number of instructions or work per instruction. -- Lawrence Crowl 716-275-9499 University of Rochester crowl@cs.rochester.edu Computer Science Department ...!{ames,rutgers}!rochester!crowl Rochester, New York, 14627
xxremak@csduts1.lerc.nasa.gov (David A. Remaklus) (09/18/90)
In article <1990Sep14.173018.10197@batcomputer.tn.cornell.edu> kahn@batcomputer.tn.cornell.edu (Shahin Kahn) writes: >The latest issue of Supercomputer Review has a little report on >a company working a "Minimum" instruction-set computer. > >What is this? Very fast boolean algebra? > >Shahin. Most of what I have heard on the MISC chip is covered by confidential disclosure agreements. So that I don't inadvertantly spill their beans I'll tell you where to e-mail to get more information. It is well worth the effort as it represents some really hot ideas and technology. Contact Mr. Phil McKinney, President of Teraplex Inc. at: mckinney@teraplex.com -- David A. Remaklus NASA Lewis Research Center Cleveland, Ohio 44135 xxremak@csduts1.lerc.nasa.gov
matloff@heather.ucdavis.edu (Norm Matloff) (09/19/90)
In article <1990Sep14.205913.2146@cs.rochester.edu> crowl@cs.rochester.edu (Lawrence Crowl) writes: >In article <1990Sep14.173018.10197@batcomputer.tn.cornell.edu> >kahn@batcomputer.tn.cornell.edu (Shahin Kahn) writes: %>The latest issue of Supercomputer Review has a little report on a company %>working a "Minimum" instruction-set computer. What is this? Very fast %>boolean algebra? >I do not know what that project is, but I once played with an instruction set >with two instructions: "increment" and "decrement and branch conditionally". I think Daniel Tabak, now at Geoge Mason University and then at Boston University (?), wrote a couple of papers on a "SISC" design -- "single instruction set computer." No, it wasn't a Turing machine. :-) I think he wrote something up in the European microprocessors journal. It also might be referenced in Tabak's book on RISC. Norm
jkenton@pinocchio.encore.com (Jeff Kenton) (09/19/90)
From article <1990Sep18.162246.19572@eagle.lerc.nasa.gov>, by xxremak@csduts1.lerc.nasa.gov (David A. Remaklus): > > Most of what I have heard on the MISC chip is covered by confidential > disclosure agreements. There was an article in one of the trade magazines about this machine. The features I remember are: . 128 bit instructions -- 64 bits to control the functional units and 2 32-bit addresses. . No registers. Everything is memory to memory. . Only 9 basic (presumably low level) instructions. The "opcode" bits directly control the hardware with no decoding. . I have no idea what the functional units are, nor the instruction set. . Typical memory requirements are exxpected to be higher than with current processors. "Less than 10 times as much." . Projected ship date is 1991 (1992?). Sounded to me like an interesting approach but without enough details to be sure. Additions and corrections invited. ----- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ----- ----- jeff kenton --- temporarily at jkenton@pinocchio.encore.com ----- ----- --- always at (617) 894-4508 --- ----- ----- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -----
davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr) (09/19/90)
The minimal instruction set is probably 1 bit opcode field. One
instruction is "add immediate and conditional branch" and the other is a
NOP to put in the delay slot.
--
bill davidsen (davidsen@crdos1.crd.GE.COM -or- uunet!crdgw1!crdos1!davidsen)
VMS is a text-only adventure game. If you win you can use unix.firth@sei.cmu.edu (Robert Firth) (09/19/90)
In article <2683@crdos1.crd.ge.COM> davidsen@crdos1.crd.ge.com (bill davidsen) writes: > The minimal instruction set is probably 1 bit opcode field. One >instruction is "add immediate and conditional branch" and the other is a >NOP to put in the delay slot. Aha! cried the dwarf, leaping on his shoulders... in that case, we can construct a CISC version with a pipeline stall, so eliminating the need for a NOP. We now have a one-instruction machine with an encoding of zero bits. Of course, a typical program might need rather a lot of them, but think how little memory they'll occupy!