[comp.arch] Multiple Instruction Sets

lindsay@gandalf.cs.cmu.edu (Donald Lindsay) (11/10/90)

(Actually, this is "The CPU with 3 brains", except that that thread
took a left turn without changing Subject.)

>> In article <42737@mips.mips.COM>, mark@mips.COM (Mark G. Johnson) writes:
>> |        SPARC CPU:   30K gates   }     all of these reside on the
>> |        MIPS CPU:    30K gates   }     same die, a 100K gate array
>> |        i286 CPU:    30K gates   }     in BiCMOS technology

It's been tried, sort of. Back in the days of CP/M, there was a
machine containing several 8-bit processors - Z80, 6502, like that.
It didn't sell well.

Besides, who wants to design someone else's machine? You'd have to
certify it, work up test suites - I suppose LSI Logic and BIT are
golden here, since they both have MIPS/SPARC expertise.

AMD already makes a 286: why don't they get into the RISC-chip-set
market by building a 286 into one corner of a glue/peripheral chip?
This would allow workstations to be PC-compatible for dead minimal
cost. If the glue chip already had a memory port (say, to do DMA)
then it wouldn't even take extra pins.

You can't trust a 286's software: applications run privileged.  So, a
chip-set 286 could be superior to using a normal 286, in that AMD
could build in bounds registers to keep it from running wild. 


-- 
Don		D.C.Lindsay