david@elroy.jpl.nasa.gov (David Robinson) (03/22/91)
I have heard a couple blurbs about Sparc International releasing a
new version of the SPARC architecture. Does anyone have any concrete
details on what things have changed from the original SPARC definition?
I assume that it will be upwardly compatible. I have also heard bits
about it being better suited for multiprocessing. Maybe a integer
multiply and divide?
Or is it just another person confusing a new implementation with a
new architecture?
-David
--
David Robinson david@elroy.jpl.nasa.gov {decwrl,usc,ames}!elroy!david
Disclaimer: No one listens to me anyway!
"Once a new technology rolls over you, if you're not part of the steamroller,
you're part of the road." - Stewart Brandmslater@cup.portal.com (Michael Z Slater) (03/24/91)
>I have heard a couple blurbs about Sparc International releasing a >new version of the SPARC architecture. Does anyone have any concrete >details on what things have changed from the original SPARC definition? >I assume that it will be upwardly compatible. I have also heard bits >about it being better suited for multiprocessing. Maybe a integer >multiply and divide? >Or is it just another person confusing a new implementation with a >new architecture? Version 8 of the spec is indeed an updated architecture definition, not just a new implementation. In fact, there are no announced implementations of version 8. The version 8 specification adds integer multiply and divide instructions. In addition, a "Store Barrier" instruction was added that requires all stores initiated before it to be completed before operation can continue. This is designed to support future multiprocessor machines that allow memory operations to occur out-of-order. Version 8 formally specifies a no-op instruction. This does not add a new opcode but is just a recommendation for which of the many possible "no operation" instructions (such as moving any register to register 0) compilers should use. This will be helpful for future superscalar implementations, since it makes it easier to identify instructions as no-ops that can be discarded. The new specification also redefines the existing 80-bit floating-point instructions to be 128-bit quad precision. The forthcoming Lightning, Pinnacle, and Viking processors presumably will include the version 8 extensions. Existing SPARC processors trap on any undefined instructions, and Sun's current operating system already emulates the new multiply and divide instructions in the trap handler. The Store Barrier instruction is simply a no-op in existing systems, which don't perform out-of-order stores. Programs using the new instructions are therefore fully compatible with existing hardware, as long as quad-precision floating-point is not used or emulation is provided. The new document also includes the reference MMU specification and recommended ASI (address space identifier) assignments. Many changes have been made to the wording to eliminate ambiguities and ensure compatibility among various implementations. The specification also adds a precise memory model, specifying a set of rules for out-of-order memory transactions, which Sun claims is important to provide portability for multiprocessor applications. Michael Slater, Microprocessor Report mslater@cup.portal.com
torek@elf.ee.lbl.gov (Chris Torek) (03/24/91)
In article <40492@cup.portal.com> mslater@cup.portal.com (Michael Z Slater) writes: >Version 8 of the spec is indeed an updated architecture definition, not just >a new implementation. ... Okay, so just how does one go about obtaining version 8 of the spec? It would be nice to have both Sprite and our kernel support multiply and divide instructions, for instance.... -- In-Real-Life: Chris Torek, Lawrence Berkeley Lab CSE/EE (+1 415 486 5427) Berkeley, CA Domain: torek@ee.lbl.gov
mslater@cup.portal.com (Michael Z Slater) (03/25/91)
>>Version 8 of the spec is indeed an updated architecture definition, not just >>a new implementation. ... > >Okay, so just how does one go about obtaining version 8 of the spec? The SPEC is distributed by SPARC International. phone 415/321-8692 or fax 415/321-8015. I don't know what the price is. Michael Slater, Microprocessor Report mslater@cup.portal.com
davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr) (03/25/91)
In article <40492@cup.portal.com> mslater@cup.portal.com (Michael Z Slater) writes: | The version 8 specification adds integer multiply and divide instructions. | In addition, a "Store Barrier" instruction was added that requires all stores | initiated before it to be completed before operation can continue. This is | designed to support future multiprocessor machines that allow memory | operations to occur out-of-order. And now we can recycle all the arguments we just had about ordering of stores to disk. "You can't run a database on a machine with out of order {x} writes." "But we do." "It will be a lot slower because you have to {y}." "it's lots faster then then the old {z} machine." "Less filling!" "Tastes great!" -- bill davidsen (davidsen@crdos1.crd.GE.COM -or- uunet!crdgw1!crdos1!davidsen) "Most of the VAX instructions are in microcode, but halt and no-op are in hardware for efficiency"