fu@uicsrd.csrd.uiuc.edu (07/21/88)
Starting multiple operations and killing off the unwanted ones, when the conditions are available, seems to be a typical trick in hardware design. For instance, start computing one or more results in parallel and kill off the unwanted ones when you have the conditions available. For the cache, you would start using the data as soon as possible and start constructing the memory access. When the hit/miss has been resolved, kill off the appropiate operation. Clearly you need to do this before something irreversible happens e.g. writing to a register, sending the request etc. The VAX 88XX cache and TB kind-off do this. ****************************************************************************** John W. C. Fu University of Illinois at Urbana-Champaign UUCP: {ihnp4,seismo,pur-ee,convex}!uiucdcs!uicsrd!fu ARPANET: fu%sneezy.csg.uiuc.edu or fu%uicsrd@a.cs.uiuc.edu CSNET: fu%uicsrd@uiuc.csnet BITNET: fu@uicsrd.csrd.uiuc.edu *******************************************************************************