mash@mips.COM (John Mashey) (10/22/90)
In article <EMV.90Oct19185644@duby.math.lsa.umich.edu> emv@math.lsa.umich.edu (Edward Vielmetti) writes: >In article <527@inews.intel.com> jsweedle@einstein.intel.com (Jonathan Sweedler) writes: > > In the February 1990 issue of IEEE Micro there is a comparison between a > 25 MHz i486 system (Compaq Deskpro 486/25, Model 650) and a Sun > Sparcstation 330 (also running at 25MHz). > >The Sparcstation 330 is perhaps the rottenest price-performance that I >can think of for Sparc models. You pay a huge premium for that big >VME cabinet, and it isn't even that big. A better price comparison >would be with a Sparcstation 1 (then) or 1+ or IPC. > > The integer spec mark (does not include the 6 floating-point SPEC > programs) for the i486 system is 13.0 and the sparc system is 12.2. > >When you quote specmarks, please quote as much as you can (all 10 numbers >would be the best). Otherwise you put yourself up to the question >"why didn't he quote the floating point numbers"? Well, 486 presentations tend to quote integer SPECs, and i860 ones SPECmarks, but the full data has been published. Here are some data points: SPEC SPEC SPEC gcc esp spi dod nas li eqn mat fpp tom INT FLT MRK SYS 13.8 12.2 8.8 5.8 5.8 16.8 11.0 9.5 7.0 4.3 13.3 6.6 8.8 1 16.2 16.6 11.1 8.2 7.6 22.2 14.5 11.3 9.6 6.6 17.2 8.9 11.6 2 ----- 12.7 11.0 10.0 6.1 12.1 9.5 12.0 12.8 9.5 7.1 11.2 9.3 10.0 3 13.8 11.6 11.4 9.5 14.0 11.2 12.6 14.7 13.1 8.2 12.3 11.6 11.8 4 ----- 18.4 18.1 14.3 16.7 20.9 23.1 18.8 15.5 15.9 18.5 19.5 16.8 17.9 5 System 1: i486, 25MHz, 128KB cache, measured 1Q90, MetaWare High C R2.2c, Silicon Valley Software FORTRAN V2.6, from Feb 1990 Intel i486 Performance, issue 1.0 System 2: i486, 33 MHz (AT&T Starserver E), 128KB cache, MetaWare High C R2.3a, SVS FORTRAN V2.8, Weitek 4167 coprocessor. (note this is NOT desktop) ---- System 3: SPARCstation1+, 25MHz LSIL SPARC, 64KB cache, from Spring90 SPEC System 4: SPARCstation 330, 25MHz Cypress SPARC, 128KB cache, Winter90 SPEC ---- System 5: (just for fun): MIPS Magnum (RC3230), 25MHz R3000, 64KB cache, Summer90 SPEC Now, FROM THE LATEST PUBLISHED DATA (I have newer stuff for >1 of these machines, but can't mention it), and X86 nubmers above are only ones I know of that are published. Also, I do know better SPARC numbers are coming: 1) Comparing systems 1 (486), 3 & 4 (SPARC), all at 25MHz: a) The 486 is usually faster (5/8), sometimes equal (1/8), sometimes slower (2/8, on eqn) than either of the 25MHz SPARCs. b) The 486 is always slower on FP 2) Comparing the 33MHz 486 (system 2) with the SPARCs: a) The 486 is always faster on integer b) The 486 beats the SS1+ on 2 of 6 FP benchmarks c) The 486 never beats the SS330 on the FP benchmarks HOWEVER, JUST TO MAKE SURE EVERYBODY READS THE FINE PRINT: 1) The systems were measured at different times. 2) The SPARCs use their standard compiler, which however, was probably reported with Beta numbers at some point, but is standard now, and these compilers are what people use (unless they use the newer ANSI C ones). 3) The Intel numbers are (quite legally) reported with their choice of compilers, of which a large number exist. I have no idea: a) Do these compilers give better-than-average, average, or worse-than-average results? (I suspect better-than-average, but I don't know.) b) In actual use, what fraction of code is compiled with these compilers? c) In actual use, what does a user actually see for performance? This depends on the mixture of compilers used. For instance, perhaps some compiler that is widely-used for code-size, debugging-help, or other features actually consumes 90% of the market, and generates code that is 10% slower than these compilers. A real user would likely see 90% of the performance shown above, which changes many of the SPARC-486@25MHz integer comparisons. 4) Of course, to be fair, when you buy a SPARC application, it may well have been compiled by an old compiler, and would have less performance. Of course, an old 486 compiler might have been used also.... 5) Note that the AT&T 33MHz 486 uses a Weitek 4167 coprocessor. a) How much difference does this make?: b) How many applications contain code compiled directly for the 4167 (which is NOT object-code compatible with the 486)? Or, if not, do they have code that dynamically chooses the 486's built-in FPU versus the 4167? Clearly, if you're running your own code on the Starserver, and doing numeric work, you might compile it for straight 4167 for max speed. 6) Note that both 486s use 128KB external caches, plus some kind of external cache controller, compared to various configurations of SPARCs. I won't try to guess at the SPARC chips' cost, except I'll bet the SS1+'s equivalent chipset costs less than the 486 alone, much less the external SRAM&stuff. 7) In any case, READ THE FINE PRINT IN THE SPEC RESULTS PAGES. THAT'S WHY IT'S THERE. If I had to summarize all of this, I'd expect that i486s, compared to SPARCs at same clock rate: are equal, or slightly faster on integer are almost always slower on floating point cost more Of course, 486s & SPARCs are both slower than R3000s at same clock rate, and all of the SPEC benchmarks, so don't take the 486-SPARC results as meaning "CISC is as fast as RISC" in general. (Certain folks have been known to over-generalize.) Of course, IBM RS/6000s have about the same integer performance as MIPS at same clock rate, and strong, if variable, FP. ========== While we're on numbers, here's a quiz. identify the following sequence of MFLOPS numbers: 1.0 1.2 1.4 Jan 89 Mar 89 Dec 89 Aug 90 ----- --------------- ------ ------ Simu- Proj- Measured..... lated ected 7.3 10.0 5.4 5.4 FORTRAN LINPACK DP 17.0 13.2 13.2 10.3 10.2 Coded LINPACK DP ANSWER: i860 LINPACK MFLOPS ratings, as shown in various versions of the the i860 Performance document (which is generally a good document, especially in recent versions). The first number (17.0 was for 50MHz, inner-loop numbers, quated at ISSCC. The next numbers show simulations at that time, followed by projections of what was expected as compilers got tuned up. All of these numbers are at 40MHz, and the newest ones are measured. MORAL: think hard about ANY vendor's (including us) predictions of performance 5-10 years from now, and take them with a grain of salt. -- -john mashey DISCLAIMER: <generic disclaimer, I speak for me only, etc> UUCP: mash@mips.com OR {ames,decwrl,prls,pyramid}!mips!mash DDD: 408-524-7015, 524-8253 or (main number) 408-720-1700 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086