andrew@frip.gwd.tek.com (Andrew Klossner) (05/28/88)
>> Support for multiprocessing via cache coherency features of cache > Lets hear about these very IMPORTANT features in detail. Anyone have > this information available to them? I have the documentation, but I'm not a cache expert and if I try to summarize this in a net article I'll probably botch it. If you're really interested, I refer you to the references mentioned in other comp.arch articles; a call to a Motorola sales office should turn them up. (Or maybe not ... has anyone not in the 88open consortium tried this? Is this material actually available to the public now?) The 88200 manual completely describes the cache coherency protocols, including some pretty complicated state diagrams. -=- Andrew Klossner (decvax!tektronix!tekecs!andrew) [UUCP] (andrew%tekecs.tek.com@relay.cs.net) [ARPA]
mslater@cup.portal.com (05/29/88)
I'm told by Motorola that the User's Manuals are still available only under
non-disclosure, and won't be publicly released until the fourth quarter.
The are "technical summaries" now available that provide general descriptions,
but not full details.
We'll have an article on the cache coherency protocols in our next newsletter.
Michael Slater Editor, Microprocessor Report 550 California, Suite 320
uucp: mslater@cup.portal.com bix: mslater Palo Alto, CA 94306
(415) 494-2677