mslater@cup.portal.com (Michael Z Slater) (07/14/89)
Since there was considerable interest expressed on the net about ferroelectric RAMs, but little data seemed to be available, I am posting the text for an article I wrote about them for the July issue of Microprocessor Report. The newsletter also has a quick primer on ferroelectric technology, which I have not included because it depends on several figures. If you would like a printed copy, send a request with your US mail address to mslater@cup.portal.com. Copyright 1989 by MicroDesign Resources Inc. Reproduced with permission. ------------------------------------------------------------------ First Ferroelectric Memories Sampled Makers scale down expectations for initial products Ferroelectric memories have been a subject of experimental interest since the 1950's, but efforts to develop commercial products have so far been unsuccessful. If the advocates of the technology are correct, however, a critical threshold has been reached in ferroelectric process technology, and a trickle of commercial products to be shipped later this year will become a flood over the next few years. Dataquest has projected that 1992 revenues from ferroelectric memories will reach $350 million, but delays in developing the technology may slow the growth of the market. Two companies have spearheaded ferroelectric (FE) technology development --- Ramtron Corporation, in Colorado Springs, Colorado with corporate roots in Australia, and Krysalis Corp., which recently moved from Albuquerque, New Mexico to Santa Clara, California. Both have developed experimental FE RAMs for use as technology development and demonstration vehicles, but none have made it into commercial production. (Ferroelectric RAMs are commonly called FRAMs, although Ramtron has trademarked this term.) Because FE technology has taken a long time to develop and requires access to costly semiconductor fabrication facilities, both companies have forged alliances with other manufacturers. Fundamental Advantages and Limitations Ferroelectric technology has some tremendous advantages. Because ferroelectric capacitors are stable storage devices, a one-transistor dynamic-RAM-like structure can function as a static RAM, requiring no refresh --- and no power --- for data retention. FRAMs provide the non-volatility offered by EEPROMs, but with full-speed write cycles and higher density. Thus, they may potentially compete with nearly all current semiconductor memory technologies, and have in fact been called "universal" or "ideal" memories. There are, inevitably, some disadvantages. While the ferroelectric process builds on a standard silicon base, it is nevertheless not a simple matter to add new materials into a semiconductor fabrication process. FRAMs also have a limited endurance --- they weaken a little with each read or write cycle. Current devices have a specified endurance of 10^10 cycles, with 10-year data retention. As the cell fatigues, retention time decreases. Unlike EEPROMs, the read cycle is destructive. This can be handled on-chip by automatically rewriting the data, but it has several implications. Whereas EEPROMs can be read indefinitely and only wear out from write cycles, both reads and writes weaken FRAM cells. The need to rewrite the data after each read access also results in a read cycle time that is twice the read access time, much like a dynamic RAM. Fortunately, the endurance level is much better than the 10^4 to 10^6 cycles offered by EEPROMs, and FRAM makers expect to increase the endurance to 10^12 cycles next year and eventually to 10^15 cycles. To put this in perspective, there are 107.5 seconds in one year, and 109 in thirty years. If a cell is read or written at a 10 MHz rate, then 10^14.5 accesses per year will be performed. The fatigue problem affects each cell individually, however, and it would be a very unusual application that would access a single memory location at this rate. Assuming that a system performs 10 million accesses per second, but that no single address is accessed more the one time out of a hundred, the number of accesses is to 10^12.5 per year or 10^14 in 30 years. Thus, an endurance of 10^10 cycles is not sufficient for replacing RAMs in general-purpose applications, but is adequate for any application that does not access any location more than ten times per second on average. An endurance of 10^15 cycles, which would allow a million accesses per second for thirty years, would be essentially infinite for all but the most pathological cases. Because reading a FRAM cell requires internal circuitry to perform a destructive read followed by an automatic write cycle, FRAMs require a synchronous chip select (CS) signal. The address is latched at the leading edge of CS, and CS must be pulsed for each access. This is not a problem for new designs, but will keep FRAMs from working in some existing designs that use an unqualified address decode to produce CS. One possible FRAM configuration is a shadow RAM, in which a conventional SRAM or DRAM cell is shadowed by an FE cell. The FE cell is written only when power is failing, and is read only at power-up, so endurance is not a problem. While this type of memory has a larger cell size than simpler structures, the cell size is much smaller than that of conventional EEPROM-based shadow memories, pioneered by Xicor. Ramtron Targets SRAMs Ramtron, founded in 1984, was the first company to pursue ferroelectric semiconductor technology. They described their first ferroelectric RAM, a 256-bit device called the FMx801, at ISSCC in the spring of 1988. This chip was fabricated in a research lab at the University of Colorado using wafers from NCR, and was not designed for volume production. Ramtron provided samples on a very limited basis, primarily to their partners. In June 1988, Ramtron teamed up with West-Germany-based ITT Semiconductors to develop commercial FRAMs. The pact calls for ITT to invest more than $6 million in Ramtron in addition to providing foundry capacity. In return, ITT gets a license to use the technology, but will pay royalties to Ramtron. ITT is a major manufacturer of ASICs for digital television and automotive applications, and is believed to be interested in the technology for these and similar applications. The first product of this venture is the FM1208, a 4-kbit (512 x 8) static FRAM, based on a 3-micron CMOS process, using a standard 24-pin SRAM pinout. First silicon was fabricated in March, and engineering samples are now being delivered to beta sites. A product evaluation kit, including samples, an evaluation board, and literature will be available late this year, and fully-qualified production samples are scheduled for April 1990. Pricing has not been set, but production pricing is expected to be comparable to EEPROMs of equivalent density. Read access time is 100 ns, and read or write cycle time is 200 ns. Endurance is rated at 1010 cycles with a 10-year retention time. The chip uses a two-transistor, two-capacitor memory cell. Maximum power consumption is only 10 uA when in standby and 16 mA when active. Smaller FRAMs, the 128 x 8 FM1008 and the 256 x 8 FM1108, will also be available, and will be made from the same mask set as the 1208. A 16-kbit device, the 1408, is now in development, with first samples expected early next year. A 256-kbit chip is scheduled for first samples in the fourth quarter of 1990. Ramtron has been aggressive in entering into technology co-development agreements with other companies. NMB Semiconductor plans to develop a 4-Mbit dynamic RAM using 0.8-micron CMOS technology and FE capacitors, based on Ramtron's technology. This device will not be non-volatile, but uses the ferroelectric material for its very high dielectric constant, which allows more charge to be stored. This is one way to address the serious scaling problems being encountered as the capacitors in dense DRAMs no longer hold enough charge for reliable operation. Ramtron will have rights to the process, but not to the chip design. Seiko-Epson is developing a high-density, non-volatile SRAM, using a one-transistor cell. Both Seiko-Epson and Ramtron will have rights to sell the resulting devices. Ramtron also has an alliance with TRW to pursue military applications, and has recently signed an agreement with Alcan Aluminum to jointly develop a high-volume FE IC production process. Ramtron is now building a small fabrication facility in Colorado Springs, using a $19.5 million equity investment from the National Electrical Contractor's Association pension fund. The facility is intended for use as a research and pilot line for technology development. Ramtron is also working with TRW to develop FRAMs for military applications. At this time last year, press reports stated that Ramtron would sample a 32K x 8 RAM, now set for early '90, by the end of '88. According to a Ramtron spokesperson, the University of Colorado fabrication facility they were using at the time was not adequate to produce production chips. Presumably, the results from ITT and Seiko-Epson will be much better. Krysalis Starts with Small Chips Like Ramtron, Krysalis has built experimental FRAMs, but has not been able to mass produce them. They made a 512-bit device, intended as an evaluation vehicle, that operated properly but required considerable off-chip control circuitry. Their next undertaking was a 16-kbit device (the K22C16) with on-chip control circuitry, which was described at this year's ISSCC. Despite press reports in the spring of '88 saying that the chip was being sampled and would be in volume production by the end of '88, it was never shipped. According the Krysalis, the ferroelectric part of the chip worked fine, but there were problems with the supporting circuitry. This chip used a charge pump to produce an 8-V write signal for the FE cells; Krysalis says they have learned how to make the chips so a 3 V signal will suffice, eliminating the need for the charge pump. Krysalis has now decided to start small --- they are making a non-volatile octal latch, the K74CF372. Each of the eight FE cells is shadowed by a regular CMOS latch to provide a continuous output signal. (Since reading the FE cell is a destructive operation, a constant output cannot be generated directly.) The FE cells and the CMOS latches are written every time the clock is pulsed. At power-up, the outputs are low until the special RECALL input is pulsed to transfer the state of the FE cells to the CMOS latches; this is the only time the FE cells are read. The RECALL input uses the pin which normally serves as the clock enable input of a 74xx377; in all other respects, the chip is pin-compatible with the 74HCT377. In future designs, a power-up detector will produce the recall pulse, making this pin available for the standard function. Maximum quiescent power consumption is 80 uA with CMOS input levels, or 1.3 mA with TTL input levels. With a 300 kHz clock signal, maximum power consumption is 12 mA. Krysalis is specifying an endurance of 1011 cycles for one-year retention. Samples will be available this month, at $25 each. Projected pricing in 100s is $8.50 in a ceramic package; volume pricing in plastic is projected to be well under $2. Krysalis has a technology development agreement with National Semiconductor, and the K74CF372 is fabricated in 2-micron CMOS using National's fabrication lines. National has not yet revealed their plans for the technology. Krysalis says that they can produce essentially any standard CMOS latch, shift register, decoder, or multiplexer chip, with a 16-week lead time. They are awaiting customer inputs on what devices are desired before expanding the product line. Krysalis expects these chips to replace DIP switches, small EEPROMs, and small battery-backed RAMs. Applications include configuration memory, instrument calibration, elapsed time meters and odometers, ID tags, encryption key storage, and radio and TV tuners. Their next product, aimed at similar applications, will be a serial-interface 4-kbit non-volatile RAM, pin-compatible with Xicor's 2404 EEPROM. They expect their pricing initially to be close to, but somewhat higher than, Xicor's. The advantages over the EEPROM product will be the fast write time and greater endurance. First samples are expected by the end of this year, with production in the first quarter of '90. Krysalis plans to build larger non-volatile memories, but they are cautious about making too many projections. Another area they plan to pursue is programmable logic, including both simpler PLDs and programmable gate arrays. One possibility is a Xilinx-like chip, but with non-volatile RAM determining the logic function so no downloading was required. Krysalis has a agreement with SCI Systems to develop a radiation-hardened 256K nonvolatile RAM. They also have agreements with 3M to develop optical applications, and with Raytheon Semiconductor to develop bipolar products with embedded FE memory. What the Future Holds Ferroelectric technology has the potential to revolutionize semiconductor memory. Volume fabrication is still only a promise, but those involved in the technology are confident that the major barriers have been overcome. If their vision is fulfilled, the DRAMs and SRAMs of the future will use FE technology. Static FRAMs may provide non-volatility essentially for free, using a smaller cell size than conventional, volatile SRAMs. FE technology may also be critical in making high-density DRAMs possible, since they provide high capacitance in a small area without requiring tricky trench structures. It is discouraging, nevertheless, to see near-term plans shift from 16- and 32-kbit RAMs to 8-bit latches and 4-kbit RAMs. The pressure is now on for Krysalis and Ramtron to get chips into volume production to prove that the technology is viable. A patent battle may be emerging as well. Ramtron claims to hold many key patents, with ten issued and another 18 applied for. They point to the $30 million they have raised in less than a year as evidence that they are well-positioned with respect to the technology. Krysalis, however, questions how broadly Ramtron's patents will apply, and points out that they too have a number of patents. ------------------------------------------------------------------ Ramtron Corporation, 1873 Austin Bluffs Parkway, Colorado Springs, CO 80918; (719) 594-4455; Fax (719) 594-4939. Krysalis Corporation, 1135 Kern Avenue, Sunnyvale, CA 94086; (408) 749-7390; Fax (408) 739-5362. ------------------------------------------------------------------ Michael Slater, Microprocessor Report mslater@cup.portal.com 550 California Ave., Suite 320, Palo Alto, CA 94306 415/494-2677 fax: 415/494-3718