gideon@nsc.nsc.com (Gideon Intrater) (02/19/91)
* * * Commercial Announcement Alert * * *
If you don't want to read a press release, please skip the
remainder of this article.
NATIONAL SEMICONDUCTOR ANNOUNCES 100-MIPS IMAGING TECHNOLOGY
WITH DIGITAL SIGNAL PROCESSING: OPENS NEW MARKETS FOR
PERIPHERALS, ROBOTICS AND MULTIMEDIA
February 15, 1991 -- National Semiconductor Corporation today
disclosed a new generation of imaging technology that achieves
an unprecedented 100 MIPS performance by combining a 64-bit
superscalar architecture with high-performance, on-chip digital
signal processing.
"Today's announcement of our newest Swordfish core
technology not only provides the highest performance available
in any embedded processor solution, but also extends the
migration path of National's core processors from 1 to 100
MIPS," said Dr. Giora Yaron, vice president of National
Semiconductor's Imaging Group.
HIGH PERFORMANCE EMBEDDED PROCESSOR MARKET
The new Swordfish core is designed for use in peripherals,
robotics and multimedia systems. It addresses the needs of the
fast developing disciplines of data compression and
decompression, pattern recognition and digital high-definition
visual presentation. Potential market segments include advanced
office peripherals such as high-end printers and print servers
which demand high resolution, PostScriptTM capability, high
speed and full color. Digital copiers and high-performance
color facsimile systems constitute another segment, and
additional application areas include combined modem, fax and
data communications, hard disk servo control feedback systems
such as robotics and machine tools, and voice compression and
video compression in areas such as HDTV, multimedia and
interactive data bases.
The forecast for growth, according to both analysts and
National Semiconductor, shows that the market for 32-bit and
64-bit RISC embedded processors will grow nearly 10 times from
1.1 million units in 1990 to 10.9 million units in 1994. Ten
percent of that growth is expected to be in the high-end segment
demanding performance above 25 MIPS. Most of this growth is
concentrated in the office peripherals segment.
"The trend is clear for desktop devices to assume multiple
functions and to require more and more powerful technology, thus
opening up new and significantly wide ranging markets," said
Yaron.
We are strongly committed to developing the technology and
product applications to take advantage of these new market
opportunities," Yaron added.
SWORDFISH TECHNOLOGY
The new Swordfish core announced today is a 64-bit
Superscalar RISC architecture that incorporates two independent
integer units, a floating-point unit, on-chip instruction and
data caches and enhanced on-chip DSP functions. The core offers
true superscalar performance, which means that its dual
pipelined integer execution units can effectively execute two
instructions per clock cycle, a significant enhancement over the
inherent RISC capability of one instruction per clock cycle.
Cast in the 0.8-micron version of National Semiconductor's
M2CMOS process, the new core design effectively connects more
than 1 million transistors.
National Semiconductor Corporation designs, manufactures and
markets high-performance semiconductor products. Headquartered
in Santa Clara, Calif., the company is a global leader in mixed
analog-and-digital technologies.
--
Gideon Intrater gideon@nsc.nsc.com
National Semiconductor, P.O.Box 3007, Herzlia B 46104, Israel
Phone: +972-52-522255, Fax: +972-52-558322mark@mips.COM (Mark G. Johnson) (02/22/91)
In article <5403@taux01.nsc.com> gideon@nsc.nsc.com (Gideon Intrater) writes: (press release regarding National Semi Swordfish chip. Includes:) > > >NATIONAL SEMICONDUCTOR ANNOUNCES 100-MIPS IMAGING TECHNOLOGY >WITH DIGITAL SIGNAL PROCESSING: OPENS NEW MARKETS FOR >PERIPHERALS, ROBOTICS AND MULTIMEDIA > >February 15, 1991 -- National Semiconductor Corporation today >disclosed a new generation of imaging technology that achieves >an unprecedented 100 MIPS performance by combining a 64-bit >superscalar architecture with high-performance, on-chip digital >signal processing. > > Thanks, Gideon. Readers are certainly very interested in this material. Here are a couple of more quotes, from the conference paper on Swordfish. Reference: R. Talmudi et al, "A 100MIPS, 64b Superscalar Microprocessor with DSP Enhancements", paper TAM 5.6, 1991 International Solid State Circuits Conference, Digest of Technical Papers, pp. 100-101. line 33| "Complex number operations, which are common in DSP applications, | are supported by instructions which execute signed 16x16 line 35| multiplication in one clock cycle and produce a 32b signed result. | Operands for these instructions may be taken either from the line 37| 16 most significant or from the 16 least significant bits of the | 32b integer registers so that real and imaginary parts of a line 39| complex number may be stored in a single register and easily | handled." | ..... | line 67| "The 4kB instruction and 1kB data caches are two-way set | associative. To keep the data cache coherent with the external line 69| memory, bus snooping logic tracks the external transactions, and | invalidates the relevant data cache line when data is modified line 71| in the external memory." -- -- Mark Johnson MIPS Computer Systems, 930 E. Arques M/S 2-02, Sunnyvale, CA 94086 (408) 524-8308 mark@mips.com {or ...!decwrl!mips!mark}