gyro@kestrel.edu (Scott Layson Burson) (05/30/91)
No doubt it's much too late, and I don't know if anyone from Intel will read this anyhow, but I can't resist explaining to whoever's listening how they could make the segmentation actually usable (IMHO). 1) With reference to the instructions that, in one instruction, load 16 bits of segment into a segment register plus 32 bits of pointer into one of the other registers: 48 bits is too long for a pointer. Create variants of these instructions that split up a 32 bit word; my guess is the best compromise would be 10 bits of segment and thus 22 bits of offset, giving 256 segments (remember, two of the segment bits are privilege level) of up to 4Mb each. 2) Add a TLB for the last several segment descriptors accessed -- 8 is probably plenty. The idea is to make it possible, usually, to do one of these segment+offset loads without having to go to memory to get the descriptor. With this combination of features, the segmentation becomes cheap enough and general enough to use liberally. Comments? -- Scott Gyro@Reasoning.COM
feustel@netcom.COM (David Feustel) (05/30/91)
What's needed even more is optional per/segment page tables. i.e. a separate page table for each segment when so desired. This would overcome the current 486 limitation that any accessible segment must be completely mapped into one 32-bit virtual address space. The implication of this limitation is that, if you want to address 6 or more segments simultaneously, no segment can be greater than 1/8th of the address space (=512megabytes). -- David Feustel, 1930 Curdes Ave, Fort Wayne, IN 46805, (219) 482-9631 EMAIL: feustel@netcom.com or feustel@cvax.ipfw.indiana.edu