lindsay@k.gp.cs.cmu.edu (Donald Lindsay) (01/08/89)
In article <296@quick.COM> srg@quick.COM (Spencer Garrett) writes: >Anybody got a reference for the DARPA Microprocessor without >Interlocked Pipe Stages (or MIPS) Core Instruction Set >Architecture specification? My copy says Core Set of Assembly Language Instructions for MIPS-based Microprocessors Version 3.2 30 October 1987 Maintained by Robert Firth Software Engineering Institute Carnegie Mellon University Pittsburgh Pennsylvania 15213-3890 (412) 268-6305 As I understand it, MIPS Corp. uses something slightly different, which is close enough that a mechanical translation is practical. Also, machines which adhere to this ISA may have differing native machine languages. (The standardization is at the assembler level, not at the binary level. For example, all those famous NOPs are generated at assembly time.) -- Don lindsay@k.gp.cs.cmu.edu CMU Computer Science --
scarter@gryphon.COM (Scott Carter) (01/12/89)
In article <3980@pt.cs.cmu.edu> lindsay@k.gp.cs.cmu.edu (Donald Lindsay) writes: >In article <296@quick.COM> srg@quick.COM (Spencer Garrett) writes: >>Anybody got a reference for the DARPA Microprocessor without >>Interlocked Pipe Stages (or MIPS) Core Instruction Set >>Architecture specification? > >My copy says > Core Set of Assembly Language Instructions > for MIPS-based Microprocessors > Version 3.2 > 30 October 1987 > > Maintained by > Robert Firth > Software Engineering Institute > Carnegie Mellon University > Pittsburgh > Pennsylvania 15213-3890 > (412) 268-6305 > The current chairman of the SAE Aerospace commitee in charge of the ISA is Terry Rasset McDonnell Douglas Astronautics Company 5301 Bolsa Avenue Huntington Beach, CA 92647 (or you can contact me, same address, 714-896-3097) >As I understand it, MIPS Corp. uses something slightly different, which >is close enough that a mechanical translation is practical. Also, >machines which adhere to this ISA may have differing native machine >languages. (The standardization is at the assembler level, not at the >binary level. For example, all those famous NOPs are generated at >assembly time.) >-- >Don lindsay@k.gp.cs.cmu.edu CMU Computer Science Actually, the ISA (Instruction Set Architecture) is (or has become) a virtual machine definition where the virtual machine rather resembles the MIPS Inc ISA. The virtual machine instructions are [mostly] specified using a syntax similar to the MIPS assembler [note: _not_ MIPS machine instructions]. A processor [or processor simulation :)] vendor provides a translator and code reorganizer for the Core-to-target translation. The virtual machine is intended primarily as a compiler [i.e. Ada] target, although people do write assembly directly in Core. The basic Core ISA is pretty well established. The major work in progress is 1) including aliasing information directives to make code reorganization more efficient; and 2) specifying the extended processor environment (exceptions, interrupts, I/O instructions, MMU/cache control, clock/timers, multiprocessor operations) in a way that is both machine-independent over the target set and low-level enough to be useful. The hope is that the Core ISA will become a military standard, essentially the 32-bit equivalent of the 1750A (some of us hope that Core will be useful outside the aerospace community). Further info on request. Scott These opinions are the opinion of the writer, and in no way reflect the position of McDonnell Douglas Inc.