alvitar@xavax.com (Phillip Harbison) (05/03/90)
There are still some good reasons to use JK flip flops. Here are a few. [1] Most JK flops are internally symetrical. The pins J,S, and Q could just as easily have been K, R, and /Q. As a result, there is little or no skew between Q and /Q. This is useful if you are trying to divide a clock by 2 and create alternate phase clocks with minimal overlap. [2] Alot of JK flops are negative edge triggered. This can be useful if your design can't spare the extra nanoseconds for an inverter. [3] JK flops can simplify state machine logic, since the designer only must generate only the transition terms. With a D flop, one also has to generate hold terms. Take the following state machine example: Inputs: A, B, and C Notation: * = and Output: Q + = or Rules: Q -> 1 if A * B * /C, / = not Q -> 0 if /A * B * C, otherwise Q(n) = Q(n-1). Solution using a JK flip flop: J = A * B * /C K = /A * B * C Solution using a D flip flop: D = (A * B * /C) + (/(/A * B * C) * Q) or D = (A * B * /C) + ((A + /B + /C) * Q) This may not seem like much additional logic, but it gets worse with more complex state machines (this example is truly trivial). -- Live: Phil Harbison, Xavax, P.O. Box 7413, Huntsville, AL 35807 Uucp: alvitar@xavax.com Bell: 205-539-1672, 205-880-8951
aj-mberg@dasys1.uucp (Micha Berger) (05/04/90)
There are several types of flip-flop. Let's list them once, and clear the whole
thing up.
RS flip flop: JK flip flop:
Inputs Outputs Inputs Outputs
R S Q Q' J K Q Q'
-------------------- --------------------
0 0 q q' No Change 0 0 q q' No Change
0 1 1 0 Set 0 1 0 1 Set
1 0 0 1 Reset 1 0 1 0 Reset
1 1 - - Not Stable 1 1 q' q Toggle
Input Outputs Input Outputs
D Q Q' T Q Q'
-------------------- --------------------
0 0 1 Reset 0 q q' No Change
1 1 0 Set 1 q' q Toggle
JK gives you the most control, but if you know that 1 1 won't come up, RS
is cheaper. D is good for memory, and T is good for counters, and other
applications where the "Toggle" description is simpler.
In addition:
latch: no clock (there can be no T or JK latches)
flip-flop: clocked
transparent: can change any time while the clock is active
(also can't be T or JK)
edge-triggered: change comes shortly after clock edge, based
on input a short time before the clock edge.
leading edge: relevent edge is 0-1 transition
trailing edge: relevent edge is 1-0 transition
--
Micha Berger
mberger1%tasha@graf.poly.edu
If nothing you try will work, try to fail.