mark@mips.COM (Mark G. Johnson) (03/09/88)
In article <9792@steinmetz.steinmetz.UUCP>, oconnor@sunset.steinmetz (Dennis M. O'Connor) says: > {referring to GE RPM-40} It's currently running 40MIPS on > a wire-wrap board. We haven't said it won't or doesn't run > faster, 40MIPS is what it was designed to do, using > conservative design rules. First, a remark. The photograph shown at ISSCC was of a motherboard/ daughterboard configuration. The daughterboard contains the RPM-40 CPU and a FP coprocessor socket, and it was a green epoxy _PC board_. It hasn't been stated (yet) how many layers of PC traces exist on that board, how many power/ground planes, or how many local bypass capacitors was on it {around or ?in? the sockets} to make the CPU happy. True enough, the motherboard into which the CPU's PC board plugged, was wire wrapped. Motherboard contained SRAM chips, a crystal, &c. Second, a question. The other DARPA core-MIPS paper at the ISSCC (a 200-MIPS GaAs bipolar device from Texas Instruments) devoted a segment of the oral presentation to chip yield. They were quite pleased to reveal their exact percentage yields to date (on this DARPA-funded project) and to give their yield projections for the next 12 months or so. Could somebody from GE tell us what the yield is on the GE DARPA core-MIPS chip? TI's data included (a) # of core-MIPS chips built to date; (b) # of them that are fully-functional, (c) trendline predictions of (b)/(a) for the near future. Thanx, -- -Mark Johnson *** DISCLAIMER: Any opinions above are personal. *** UUCP: {decvax,ucbvax,ihnp4}!decwrl!mips!mark TEL: 408-991-0208 US mail: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
oconnor@sungoddess.steinmetz (Dennis M. O'Connor) (03/09/88)
An article by mark@mips.COM (Mark G. Johnson) says:
] In article <9792@steinmetz.steinmetz.UUCP>, oconnor@sunset.steinmetz
] (Dennis M. O'Connor) says:
] > {referring to GE RPM-40} It's currently running 40MIPS on
] > a wire-wrap board. We haven't said it won't or doesn't run
] > faster, 40MIPS is what it was designed to do, using
] > conservative design rules.
]
] First, a remark. The photograph shown at ISSCC was of a motherboard/
] daughterboard configuration. The daughterboard contains the RPM-40
] CPU and a FP coprocessor socket, and it was a green epoxy _PC board_.
] It hasn't been stated (yet) how many layers of PC traces exist on
] that board, how many power/ground planes, or how many local bypass
] capacitors was on it {around or ?in? the sockets} to make the CPU happy.
] True enough, the motherboard into which the CPU's PC board plugged,
] was wire wrapped. Motherboard contained SRAM chips, a crystal, &c.
(* FLAME ON *)
Do NOT imply that I am wrong about something this basic. You will
look like an idiot if you do. I HAVE THE PICTURE FROM ISSCC RIGHT
IN FRONT OF ME. THE BOARD IS A STANDARD MUPAC WIRE-WRAP BOARD
FOR THE VME BUS. I have also touched and seen the actual board.
IF I SAY IT'S WIRE-WRAP, IT IS. The RPM40 has yet to be put
on ANY pc-board, much less a multi-layer one. Which, by the way,
would be made of POLYIMIDE, NOT EPOXY. For performance, of course.
(* FLAME OFF *)
] Second, a question. The other DARPA core-MIPS paper at the ISSCC
] (a 200-MIPS GaAs bipolar device from Texas Instruments) devoted a
] segment of the oral presentation to chip yield. They were quite
] pleased to reveal their exact percentage yields to date (on this
] DARPA-funded project) and to give their yield projections for the
] next 12 months or so.
Could this be because GaAs has a CREDIBILITY problem ? Like,
no one believes you can get ANY yield at all with it ? THAT'S
why TI is willing to talk about it : THEY HAVE TO.
] Could somebody from GE tell us what the yield is on the GE DARPA
] core-MIPS chip? TI's data included (a) # of core-MIPS chips built
] to date; (b) # of them that are fully-functional, (c) trendline
] predictions of (b)/(a) for the near future.
The RPM40 is built with GE's standard AVLSI process. We'll release
yeild figures on it WHEN HELL FREEZES OVER. Go ask Intel or
Motorola what their yeilds are, see what answer you get.
It is PROPRIETARY INFORMATION. Yield almost always is.
] Thanx,
] -Mark Johnson *** DISCLAIMER: Any opinions above are personal. ***
--
Dennis O'Connor oconnor%sungod@steinmetz.UUCP
ARPA: OCONNORDM@ge-crd.arpa
(-: The Few, The Proud, The Architects of the RPM40 40MIPS CMOS Micro :-)phil@amdcad.UUCP (03/10/88)
An article by mark@mips.COM (Mark G. Johnson) says:
] First, a remark. The photograph shown at ISSCC was of a motherboard/
] daughterboard configuration. The daughterboard contains the RPM-40
] CPU and a FP coprocessor socket, and it was a green epoxy _PC board_.
Sounds like an adaptor from a PGA (or LCC, etc) to a standard WW board,
which tend to assume the world is DIPs.
Gee, this isn't net.flame, is it?
--
300 Mb on a Sun-3/60 for $2,300, quantity 1!
I speak for myself, not the company.
Phil Ngai, {ucbvax,decwrl,allegra}!amdcad!phil or phil@amd.com