davidt@psuhcx.psu.edu (Thomas S. David) (04/08/90)
Hi out there... I was wondering if anyone out there knew what technology was used in the IBM 16M DRAM which was first announced sometime in FEB 1990. i.e., specifically interested in knowing gate lengths etc., I guess TI announced a 16M DRAM too a few days after this. I hope this information is not classified, I need the info for a class. Thanks in advance, Tom. ---- E-mail dst@psuecl or dst@ecl.psu.edu or davidt@hcx.psu.edu or davidt@psuhcx or t1d@psuecl2 or ...!psuvax1!hcx.psu.edu!davidt
pi@maserati.isi.edu (Jen-I Pi) (04/08/90)
In article <2323@psuhcx.psu.edu>, davidt@psuhcx.psu.edu (Thomas S. David) writes: > Hi out there... > I was wondering if anyone out there knew what technology was used > in the IBM 16M DRAM which was first announced sometime in FEB 1990. i.e., > specifically interested in knowing gate lengths etc., I guess TI announced > a 16M DRAM too a few days after this. I hope this information is not > classified, I need the info for a class. > > Thanks in advance, > Tom. I don't have the exact info about this. But based on the fact that Japanese is able to fab 4M and 16M DRAM in 0.8um and 0.5um CMOS respectively in feature size, I would guest IBM's technology should be around 0.5um, give or take 0.1um. Jen-I pi@vlsi-cad.isi.edu :-) MOSIS Project, USC/ISI
raje@dolores.Stanford.EDU (Prasad Raje) (04/09/90)
In article <2323@psuhcx.psu.edu> davidt@psuhcx.psu.edu (Thomas S. David) writes:
I was wondering if anyone out there knew what technology was used
in the IBM 16M DRAM which was first announced sometime in FEB 1990. i.e.,
specifically interested in knowing gate lengths etc., I guess TI announced
a 16M DRAM too a few days after this. I hope this information is not
classified, I need the info for a class.
You can get detailed info from the ISSCC Technical Digest 1990, pp 232.
Here is some brief information anyway -
Technology: 0.5um CMOS
cell type: trench
cell size: 4.13 um^2
die size: 140.9 mm^2
cell capacitance: 100 fF
access time: 50 ns
fast page access: 16 ns
error correction: single error correct/double error detect
redundancy: (is present, kinda hard to describe
without also describing the array layout)
supply voltage: either 5 or 3V external
I must point out that 16M DRAMS were announced by Mitsubishi, NEC,
and Toshiba at ISSCC 89, one year before IBM.
Prasadkyriazis@iear.arts.rpi.edu (George Kyriazis) (04/09/90)
In article <2323@psuhcx.psu.edu>, davidt@psuhcx.psu.edu (Thomas S. David) writes: > Hi out there... > I was wondering if anyone out there knew what technology was used > in the IBM 16M DRAM which was first announced sometime in FEB 1990. i.e., > specifically interested in knowing gate lengths etc., I guess TI announced > a 16M DRAM too a few days after this. I hope this information is not > classified, I need the info for a class. > > Thanks in advance, > Tom. I know that the IBM design uses trench-type capacitors for thier cells. This means that the cell capacitor is extended INTO the silicon to increase capacitance per unit area. The japanese designs, place the capacitor in the form of a multi-platter hard disk above the cell. the IBM "trech" design is more difficult to fabricate than the other, but I guess they succeeded. ---------------------------------------------------------------------- George Kyriazis kyriazis@turing.cs.rpi.edu kyriazis@rdrc.rpi.edu kyriazis@iear.arts.rpi.edu