P.Rocha@cs.ucl.ac.uk (Paulo V Rocha) (12/07/90)
The most recent publication about the circuit seems to be
"Design, Fabrication and Evaluation of a 5-inch Wafer Scale
Neural Network LSI Composed of 576 Digital Neurons" by
M.Yasunaga, et.al., Proc.IJCNN'90(San Diego) pp.II-527.
I also received some details from a pamphlet probably distributed at
Hitachi's technology fair in New York.
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Neuron circuit: Completely digital circuit with learning function.
Architecture: Time sharing digital bus
Dual networks for learning
Performance of learing circuits: 2.3 GCUPS
Neumber of neurons: 144 neurons per wafer
1152 neurons per system
Neuron output: 9 bits
Synapse weight: 16 bits
Process: 0.8 micron CMOS gate array
Wafer size: 5" diameter
System size: 30 cm x 21 cm x 23 cm
Power consumption: ~50 Watt
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The circuit uses a single bus and the claimed performance is a peak
figure of operational units (multipliers and adders). Real performance
can be much less.
Each neuron has only 64 synapses because the the design uses gate array
technology and memory in this case is very expensive.
The neurocomputer has about 70 K synapses and 1 K neurons.
Thanks again to everybody.
Paulo (University College London)