horst@avior.crhc.uiuc.edu (Robert Horst) (07/30/90)
In article <sacmZI_00hMNQmYF0k@cs.cmu.edu> Daniel.Stodolsky@CS.CMU.EDU writes: >IDEA: Why not voltage domain multiplex? On a given pin, one signal >could come in at either -3 or +3 volts for 0 and 1, and a second >signal could come in at -1 or +1 volts for 0 and 1. A little extra >logic would be needed to decode the signal, but one could get a >doubling of the number of signals for a given packaging scheme... Those interested in voltage-multiplexing may wish to read the following reference: A. Khan, L. Yue, R. Horst, "An N:1 Time-Voltage Matrix Encoded Transmission System", PROC. 1989 BIPOLAR CIRCUITS AND TECHNOLOGY MEETING, Sept 1989. ABSTRACT: New encoder and decoder circuits use multiple-valued ECL and time-multiplexing to ease IC pinout limitations. Each pin can transmit or recieve up to eight bits of information in one clock cycle. Each physical pin becomes 8 "virtual pins" by 4:1 time multiplexing and 2:1 voltage multiplexing. The voltage multiplexing uses four discrete voltage levels of -Vbe, -2Vbe, -3Vbe and -4Vbe. Special voltage reference circuits provide sufficient noise margin despite possible temperature variations between encoder and decoder. The circuits were SPICE simulated with a generic ECL process (now fairly obsolete). Total delay for encoder plus decoder ranged from 1.1 ns to 3.4 ns. The paper gives schematics of the encoder and decoder circuits, and some of the timing waveforms. Several patents are pending on the new circuits. Robert Horst Tandem Computers Incorporated and Center for Reliable and High Performance Computing University of Illinois Center horst@bach.crhc.uiuc.edu