sgolson@pyrite.East.Sun.COM (Steve Golson) (03/15/90)
In article <36999@mips.mips.COM> mark@mips.COM (Mark G. Johnson) writes: > Motorola 68030 max clock period = 80 nanoseconds (12.5 MHz) The on-chip caches of the 68030 (and 68020) use 4T RAM cells that must be periodically refreshed. Anyone from Moto want to comment on what other dynamic logic they used? Steve Golson sgolson@East.sun.com golson@cup.portal.com Trilobyte Systems -- 33 Sunset Road -- Carlisle MA 01741 -- 508/369-9669 (consultant for, but not employed by, Sun Microsystems) "As the people here grow colder, I turn to my computer..." -- Kate Bush
baum@Apple.COM (Allen J. Baum) (03/17/90)
[] >In article <132903@sun.Eng.Sun.COM> petolino@sun.UUCP (Joe Petolino) writes: I saw an interesting idea >in a paper about the SPUR cache - it proposed using dynamic RAM cells for an >on-chip I-Cache (to save area), If it's what I'm thinking of, its a cute idea. Guarantee that the 'valid' bit decays before any of the others, and its easy. >Latches *are* static, at least the ECL ones that you'd find in a Cray. Many of the latches found in CMOS are not. Its quite common to make a master- slave flip-flop out of a dynamic stage, and a static stage. Then, the clock can be stopped (but only during one of the phases). -- baum@apple.com (408)974-3385 {decwrl,hplabs}!amdahl!apple!baum
jesup@cbmvax.commodore.com (Randell Jesup) (03/19/90)
In article <36999@mips.mips.COM> mark@mips.COM (Mark G. Johnson) writes: >In CMOS microprocessors, dynamic logic is used all over the place. That's >one of the reasons why there is a datasheet spec for minimum clock frequency: >to refresh these dynamic nodes. Generally, microprocessor circuits are >designed to refresh dynamic nodes every cycle. A quick and incomplete >peek at databooks reveals: Not everyone goes dynamic. The RPM-40 was fully static, on purpose. This makes debugging a processor easier, and makes certain things simpler. It also makes the chip less susceptible to radiation-caused-upset, and deterioration. (The RPM-40 was 1.25u CMOS). -- Randell Jesup, Keeper of AmigaDos, Commodore Engineering. {uunet|rutgers}!cbmvax!jesup, jesup@cbmvax.cbm.commodore.com BIX: rjesup Common phrase heard at Amiga Devcon '89: "It's in there!"
ccplumb@lion.waterloo.edu (Colin Plumb) (03/19/90)
>> I saw an interesting idea >> in a paper about the SPUR cache - it proposed using dynamic RAM cells for an >> on-chip I-Cache (to save area), In article <39538@apple.Apple.COM> baum@apple.UUCP (Allen Baum) writes: > If it's what I'm thinking of, its a cute idea. Guarantee that the 'valid' bit > decays before any of the others, and its easy. That is *sneaky*. Now, refresh the entry in case of a cache hit. If the entry hasn't been used in a few milliseconds, it will be purged. Not-recently-used! It may be impractical for other resaons, but it has serious hack value. -- -Colin
baum@Apple.COM (Allen J. Baum) (03/20/90)
[] >In article <1690@east.East.Sun.COM> sgolson@pyrite.East.Sun.COM (Steve Golson) writes: >The on-chip caches of the 68030 (and 68020) use 4T RAM cells that must be >periodically refreshed. If the cells used by the 680x0 are the same as those used in their 88200, then they are not dynamic. There are 4 transistors, and 2 pullup resistors. Most 6T cells use pullup transistors, because they're smaller. Moto's process has a high resistance poly layer, and the two resistors are place right on top of the transistors, so they take no space (except in the third dimension). -- baum@apple.com (408)974-3385 {decwrl,hplabs}!amdahl!apple!baum
raje@dolores.Stanford.EDU (Prasad Raje) (03/20/90)
> In article <39538@apple.Apple.COM> baum@apple.UUCP (Allen Baum) writes: > > If it's what I'm thinking of, its a cute idea. Guarantee that the 'valid' > > bit decays before any of the others, and its easy. > > That is *sneaky*. Now, refresh the entry in case of a cache hit. If > the entry hasn't been used in a few milliseconds, it will be purged. > Not-recently-used! It may be impractical for other reasons, but it has > ^^^^^^^^^^^^^ > serious hack value. > -- > -Colin ( The suggestion is to use dynamic storage for the valid bit and rely on its decay to purge unused entries in the cache ) Unfortunately this wont work, for this "other" reason. The rate of decay of a DRAM memory cell (essentially the charge leakage from the storage node through a reverse biased p-n junction) is very difficult to control accurately. After the junction leakage has been reduced to the order of a few pico amps per micron^2 it is very difficult to control to even 100% accuracy. The refresh rate of the order of a few milliseconds is really a safe lower limit on how long the charge will reliably be stored on the node. There have been recent DRAMs made with as long as 1 second retention times. Assuming a storage capacitor of C = 50 fF and a leakage current of i = 10 pA using i = C dv/dt, the rate of decay is 0.2 V/ms So even if you were able to control i very accurately to 10pA, the cell voltage have decayed only to 4.8V from 5V after 1ms. When the time comes to decide if the valid bit has "faded away" it will be very difficult to make a decision in a time that is of the order of sucessive cache accesses. In brief, a highly uncontrollable technology-level parameter would determine a architecture-level parameter viz. the replacement strategy of the cache. I realize this is straying away from comp.arch, but this thread has been here for a while now. cheers Prasad
tommyk@cs.glasgow.ac.uk (Tommy Kelly) (03/21/90)
Does anyone know if failing to meet the minimum clock freq. on a dynamic device could actually DAMAGE the part? tk -- ================================================================================ Disclaimer: "You can't pin that wrap on me." ================================================================================
jgk@osc.COM (Joe Keane) (03/21/90)
Hmm, if you can guarantee that bits only decay in one direction (say 1->0) then all you have to do is add a few check bits to each cache entry. When one or more of the data bits decays, you'll know the entry is invalid. Of course, the check bits might decay even though the data bits are OK, in which case you'd also say the entry is invalid.