md89mch@cc.brunel.ac.uk (Martin Howe) (06/28/90)
Hi everybody.
I would just like to say thanks to all who replied to my posting.
As expected, there were almost as many different ways of organising
a chip design procedure as respondents, but the way which I described
in my original posting seemed to be used fairly often and even some
people at one of the *big* companies said that it is what they did
for two *very* popular CPUs, so I suppose that it's as good a way as any.
VHDL ?
Well, opinion ranged from "only use it for defence contracts" to
"use it or go under". People did not seem to like VHDL because of
it being so cumbersome (suprise, suprise :-) but it is useful for
going top-down to logic synthesis, provided gate arrays or silicon
compilers are what you can use.
Cadence's Verilog was mentioned and appears to be very popular;
since Cadence have "opened" Verilog as a standard, and some people
are writing or considering writing Verilog <-> VHDL translators,
it could well be that people will design with Verilog (or the
system most suited to their needs) and use VHDL as an interface
to foundries, or if DoD work is being done.
For myself, I have been discussing the matter with people at
Brunel, and have been advised to use the Ella system, since VHDL
is lousy for custom VLSI; it's basically a glorified *logic* simulator and
meant more for gate-arrays and the like and it is VERY difficult
(I am told) to make your own macros, so that VHDL is next to useless
for low-level transmission-gate-riddled full-custom logic.
In any case, as the UK MOD is analogous to the US DoD and
Ella is the UK MOD analogue of VHDL; an Ella-user should
have no trouble with UK MOD employment in VLSI design.
What I wanted ideally is a top-down design tool that starts
with a behavioural (RTL) architecture description (preferably
with graphic input of initial high-level architecture if
not to be completely synthesised from the RTL version) that
helps you down to floor-planning stages for full-custom VLSI.
It should also serve as a floor-plan manager tool, check
inter-block interfaces, current approx. block & chip size, etc.
Although Brunel gets Cadence (Solo 2000) next year, I have to
do all of the above manually and use the MAGIC VLSI editor. Yuk !
Once again, thanks to all who replied.
Footnote (for those who asked in mail) --
Normally, we at Brunel get our chips fabricated by ES2 from
tapes sent to them. I am waiting for our full-custom
term-assessment chips to come back (horror :-).
Regards,
Martin.
--
- /| . . JCXZ ! MOVSB ! SGDT ! iAPX ! | In space, no-one can hear you kill
\`O.O' . Martin Howe, Microelectronics| an ALIEN
={___}= System Design MSc, Brunel U. | - from "Torquemurder"
` U ' Any unattributed opinions are mine -- Brunel U. can't afford them.