lindsay@gandalf.cs.cmu.edu (Donald Lindsay) (06/21/91)
I notice that the new i860 is built with a 3-level-metal process. I recall that Motorola promised to build the 88110 this way, and someone posted here expressing disbelief. So, is the i860 really the first? And how many of the upcoming superscalars will be three layer? -- Don D.C.Lindsay Carnegie Mellon Robotics Institute
jackk@leland.Stanford.EDU (Jack Kouloheris) (06/22/91)
In article <13560@pt.cs.cmu.edu> lindsay@gandalf.cs.cmu.edu (Donald Lindsay) writes: >I notice that the new i860 is built with a 3-level-metal process. > >I recall that Motorola promised to build the 88110 this way, >and someone posted here expressing disbelief. > >So, is the i860 really the first? And how many of the upcoming >superscalars will be three layer? >-- >Don D.C.Lindsay Carnegie Mellon Robotics Institute The RS/6000 chipset was built using a 3 layer metal process...the third layer, in this case, being used for power distribution and attachment to the C4 flip-chip solder bumps. (The I/Os are located are distributed in the middle of the chip rather than being restricted to the periphery)
roger@gimli.inmos.co.uk (Roger Shepherd) (06/22/91)
In article <13560@pt.cs.cmu.edu>, lindsay@gandalf.cs.cmu.edu (Donald Lindsay) writes: |> I notice that the new i860 is built with a 3-level-metal process. |> I recall that Motorola promised to build the 88110 this way, |> and someone posted here expressing disbelief. |> So, is the i860 really the first? And how many of the upcoming |> superscalars will be three layer? The T9000 transputer (which is superscalar - with a vengence) uses a 3-level-metal process. I would expect a significant number of the next generation of processors to be implemented on three (or more) layer metal processes. High density, high connectivity, three layer processes, like that used for the T9000, offer very high transistor density; they are very attractive for large scale logic devices. Roger Shepherd - roger@inmos.co.uk or roger@inmos.com
wilkes@mips.com (John Wilkes) (06/22/91)
In article <13560@pt.cs.cmu.edu> lindsay@gandalf.cs.cmu.edu (Donald Lindsay) writes: > >So, is the i860 really the first? And how many of the upcoming >superscalars will be three layer? The MIPS R6000 ECL processor, R6010 floating point controller and R6020 system bus chip are all three layer metal. -wilkes <wilkes@mips.com>
miyazaki@taichung (Takeshi Miyazaki) (06/23/91)
Three-Level Metal for ECL (R6000) is not intresting. ECL Gate Array is built using Three-Level since several years ago. Because of large power consumption. But Three-Level Metal for CMOS is intresting. Is is also for power line? Takeshi Miyazaki miyazaki@ee.princeton.edu
ram@shukra.Eng.Sun.COM (Renu Raman) (06/23/91)
In article <4977@spim.mips.COM> wilkes@mips.com (John Wilkes) writes: >In article <13560@pt.cs.cmu.edu> lindsay@gandalf.cs.cmu.edu (Donald Lindsay) writes: >> >>So, is the i860 really the first? And how many of the upcoming >>superscalars will be three layer? > >The MIPS R6000 ECL processor, R6010 floating point controller and R6020 >system bus chip are all three layer metal. Many ECL processes have had 3LM for sometime. What D. Lindsay was refererring to is CMOS components (some current ECL and GaAS use 4 layers of metal interconnect). The new PA components are in a 1.0 micron 3LM process. >-wilkes <wilkes@mips.com> -- -------------------------------- Renukanthan Raman ARPA:ram@sun.com M/S 16-11, 2500 Garcia Avenue, TEL :415-336-1813 Sun Microsystems, Mt. View, CA 94043