fay@encore.UUCP (03/31/87)
In article <237@winchester.mips.UUCP> mash@winchester.UUCP (John Mashey) writes: >In article <948@spar.SPAR.SLB.COM> freeman@spar.UUCP (Jay Freeman) writes: >> >>How about special floating-point instructions to support "cortic" (have I >>got that spelled right?) algorithms for transcendental functions? (I > >I think it's "quartic", and I think there may be some justification >for them, depending on the silicon tradeoffs, i.e., does it cost you >time in add or multiply to put the quartics on. Depending on the >target applications, it may or may not be worth it. >...... Are you all talking about CORDIC (Coordinate Rotation Digital Computer) a la Ramamoorthy? If so, I don't understand the question. If one has an FPU with transcendentals, one doesn't need (or want) Cordic algorithms. If there is no FPU (I assume this is what is being discussed), and one wants to implement transcendentals, I doubt whether one would want to use Cordic method, since it is _extremely_ iterative and unless there was a very large on-chip cache, would eat up bandwidth like crazy. If one decided anyway to implement Cordic method, there are _no_ special instructions necessary to do so (which is why it's so neat - I wrote it for both a PE32 and a 6502). The entire algorithm can be implemented with one table look-up and successive bit shifts, increments and decrements, yeilding hyperbolic functions, sines, arctans, etc. This is also the reason it is such a great method for implementation in silicon (I believe there was a report on such a chip in IEEE Spectrum or Computer last spring) -- it can do transcendentals in a few cpu cycles (versus 68881: FATANH=693 cycles, FLOGN=525, FCOS=391, you get the point). Anyone who can tell me why these chips (1) weren't developed years ago and (2) aren't standard on every medium-size architecture with floating point deserves a beer. Peter Fay Research Encore Computer Corp. {allegra decvax ihnp4 linus okstate princeton pur-ee talcott}!encore!fay
baum@apple.UUCP (04/01/87)
-------- [] >Anyone who can tell me why these chips (1) weren't developed years ago and >(2) aren't standard on every medium-size architecture with floating point >deserves a beer. HP probably has the most sophisticated versions of the CORDIC algorithms around. CORDIC has been used in all of the HP calculators, and the code has been tweaked by no less than Prof. Kahan (of IEEE FP standard fame). HP did build a CORDIC FP processor box for their 2100 series of minicomputers, but no one bought it, so it was dropped. I think the main reason that no one has done a CORDIC chip is that the hardware and datapaths required are an addition to the multiplier and adder that the normal FP functions use. Doing it with Taylor series adds some sequencing logic or more microcode, and I guess that isn't nearly so bad. Its a tradeoff, of course. The market for high performance trig function FPUs has got to be smaller than add/sub/mul/div, so no one has gone for the niche market. There is also much less expertise (much less exposure) to the cordic algorithms, and their subtleties. -- {decwrl,hplabs,ihnp4}!nsc!apple!baum (408)973-3385