andy@rocky.STANFORD.EDU (Andy Freeman) (11/10/87)
In article <6681@apple.UUCP> bcase@apple.UUCP (Brian Case) writes: >In article <230@usl-pc.UUCP> jpdres10@usl-pc.UUCP (Green Eric Lee) writes: [Eric asks how expensive the adder in the register access path is. He suggests shift-registers as one alternative. He wonders if letting the compiler get to all the registers at once, the MIPS approach, might be better.] >Well, that's a lot of stuff for one posting. First off, the adder in >the register addressing path doesn't cost much, in the current implementation, >other than silicon area; reason: the chip does register write before read, >and the write must complete before reads can be done so that an extra level >of forwarding (bypassing is another term often used) can be avoided. So, >while the write is being done, we might as well do something useful like >an address add. Machines like Berkeley RISC II (and I suspect SUN SPARC) >simply integrate the "add" into the decode tree. This is somewhat less >expensive, but the idea is the same. I don't know about the AMD chip, but if the SPARC works the way I think it does, it doesn't need an adder to pick the right register out of the register file. The top two bits tell whether the register is global (8), from the previous window (8), or from the current window (16). The bottom bits select the register within the group. Thus the top two bits decide which bank to access (they select a bank pointer which is changed by save/restore for non-globals). I've heard that the Berkeley people had a way to eliminate the add's contribution to register access time, but, as Brian mentions, it may not have made any difference as the critical path was elsewhere. -andy -- Andy Freeman UUCP: {arpa gateways, decwrl, sun, hplabs, rutgers}!sushi.stanford.edu!andy ARPA: andy@sushi.stanford.edu (415) 329-1718/723-3088 home/cubicle