[comp.arch] WISC info

koopman@a.gp.cs.cmu.edu (Philip Koopman) (06/03/88)

In article <325@nyit.UUCP>, tmg@nyit.UUCP (Tom Genereaux) writes:
> I have seen adverts for a system that appears to be similar from
> WISC Machines in Ca. Sorry, don't have prices or much more information
> than that, but at least part of the design was done by Phil Koopman.
> Any additional information would be appreciated(sp!).
> 			Tom Genereaux
> 			NYIT Computer Graphics Lab
> 			philabs!nyit!tmg

WISC Technologies makes two machines: the CPU/16 and the CPU/32.

Both machines are two-stack, zero-operand machines.  They have RAM-based
microcode memory, so instructions can be changed for different environments,
and the user can add additional instructions.  The CPU/16 is mostly
a proof-of-concept machine, and is useful for learning how to microcode.
The CPU/32 is the "industrial-strength" version.  It features single-cycle
execution (one instruction per memory cycle -- two micro-cycles per
memory cycle) with each instruction having both an opcode and a jump
field.  This means that subroutine calls, subroutine returns, and
unconditional branches come "for free" when combined with any opcode.

Primary application areas are real-time control,
expert systems, and functional languages.
Preliminary investigations suggest good performance in conventional
languages as well.  Obviously, the stack model of computation
is well suited for Forth.  However, since the WISC machines have
writable microcode memory, they are not "just" Forth machines.

For more information, please contact:

  Dr. Glen Haydon
  President, WISC Technologies
  19500 Skyline Dr.
  Box 429, Star Rt. 2
  La Honda, CA  94020
  telephone: (415) 747-0760

I'll be in and out (mostly out) for the rest of the summer, so I may take
1 to N weeks replying to e-mail (and I may not be able to reply at
all if you have a difficult usenet path to backtrack.)  Best bet
is to contact Dr. Haydon to get information.

I am short of time now, but I'll be happy to participate in
a writable instruction set/stack machine/etc. debate on comp.arch this
coming fall.