abaum (Allen Baum) (05/09/91)
(D. Richard Hipp) writes: >I once proposed an architecture that featured "2.5" addresses... > Each instruction contains two register numbers, plus one extra bit >which indicated whether the ... (destination) should be the >same as A or should be register zero (the accumulator) >This was only an idea, and was never tested. I would be interested to hear >if John Van Zandt, or anyone else, has ever looked at this addressing scheme >and what they found after looking at it for a while. The ATT CRISP has instructions of this form, as did the Lawerence Livermore Labs S-1 machine.
johnv@sequent.com (05/09/91)
>>From: firth@sei.cmu.edu (Robert Firth) >>Subject: Re: Clarification on 3 Addr vs 2 Addr Archs >>Date: 8 May 91 13:08:16 GMT >> >>Sigh. Let me point out first that one cannot decide which >>architecture is "best" in isolation. It is necessary to >>consider application domain, programming language, language >>use styles, compiler effectiveness, and a host of hardware >>issues. I agree with all of this but the last ... that hardware issues must be considered. The idea of an instruction set is that it must be capable of being implemented and realized (using the Blaauw nomenclature) with many different ways. Take for example the VAX and the IBM 360 instruction sets. Or even the MIPS instruction sets which have now had at least 4 different implementations in several different technologies. An instruction set is just a language for describing the 'meaning' of a program, which in turn is a language for describing a solution to a problem. The effectiveness of the languages for being mapped to from the next higher up languaage is what should be considered. -- John Van Zandt ------------------------------------------------------------------------- E-mail: johnv@sequent.com V-mail: (503) 578-3136 P-mail: Sequent Computer Systems, 15450 SW Koll Pkwy, Beaverton, OR 97006