[comp.arch] Definition of "imprecise interrupt"

roginski@ogcvax.ogc.edu (Krist Roginski) (06/24/88)

I thought I knew, but recent discussion has given me doubts.
It seems like a beginner-type question is in order.

I thought it meant an interrupt where you couldn't point to a specific
spot in the code and say "restart from here".

By this definition, the Am29000 doesn't have precise interrupts, as it
stashes all the parameters of a load/store in special registers and
proceeds, stalling if necessary on a load.  Thus, if you could give it
instructions and live in the on-chip registers, you could keep going
essentially forever without satisfying the load/store, and have no idea
where in the code that instruction was issued.  (It could have been
paged out for all the processor cares.)

Another interpretation that some recent discussion seemed to imply is
an interrupt where the state of the processor can't be saved and
restored completely.

By this definition, the 29000 does have precise interrupts, as all the
registers in question are visible to supervisor mode and documented,
and can be saved and restored.

The Inmos transputer, in contrast, doesn't have this sort of precise
interrupts.  Its idea of an interrupt is somewhat different from the
usual, but basically, a "high priority" process can pre-empt a
low-priority one, but can only return to the same process it pre-empted
(well, it's possible to get around, with serious trickery, but not if
you follow Inmos's rules).

Which of these definitions, if any, is right?

Many thanks.
-- 
	-Colin (plumbc@admin.ogc.edu, posting from a friend's account)