gerry@zds-ux.UUCP (Gerry Gleason) (11/10/89)
In article <1477@aber-cs.UUCP> pcg@cs.aber.ac.uk (Piercarlo Grandi) writes: > . . . My champion as to this is the >CRISP thing: if I remember correctly the chip complexity of the CRISP and >the MIPSco chips is exactly the same, at 170k, speed is not that different, >factoring out technology, and the architectures are as different as they can >be. CRISP exists? I thought AT&T dumped that project. Is someone else making them? But your right, it's a great architecture. Simple where it counts but not impossible for anyone but a compiler to write code for. I got to make UNIX run on early silicon of this processor, so I have some experience with it. Gerry Gleason
pasek@ncrcce.StPaul.NCR.COM (Michael A. Pasek) (11/10/89)
In article <2725@brazos.Rice.edu> preston@titan.rice.edu (Preston Briggs) wrote: >[stuff about how many registers you need deleted] >...Separate load-store instructions allow lower cost of access >to non-registered variables. Why? Imagine trying to add from memory >to a register. A CISC version might be > ADD r5,0(r8) ; load from adress specisfied from r8 > wait for memory, doing > nothing much in the meantime > add the value to r5 > throw away the value you just waited for. > cost = 1 or 2 + memory acess time >[and promotes the RISC version as:] > LD r7,0(r8) ; load from adress in r8 into r7 > . ; do some useful work while waiting for memory > ADD r5,r6,r7 ; r5 := r6 + r7 > cost equals 2. Additionally, the old value of r6 is still > around, and the value from memory is handy if we need it. I don't know if I'm just stupid, but on the machine I work with, the "CISC" example takes a total of ONE cycle, assuming that the next instruction does not reference R5, and is not contained in the memory location referenced by R8. Also, in the "RISC" example, the "useful work" that may be done would have the same restrictions as the "CISC" version (no reference to R7, and the instructions cannot be in the memory location referenced by R8). Finally, the "throw away" of the value we just waited for can be avoided by coding the "RISC" example on the "CISC" machine, with the same results: it takes 2 cycles (if you do that "useful work" in between the two instructions). Anyway, I think the RISC/CISC battle will only be a philosophical argument (or perhaps a religious war), and the real decision of which is best will be made on a case by case basis by the implementer(s) of the solution(s) to a specific problem (or set of problems). If one actually is better than the other, the marketplace will decide (maybe). M. A. Pasek Switching Software Development NCR Comten, Inc. (612) 638-7668 CNG--er--PU4 Port Devel. 2700 N. Snelling Ave. pasek@c10sd3.StPaul.NCR.COM Roseville, MN 55113