[comp.arch] Slow simulations

gnu@hoptoad.UUCP (04/17/87)

In article <16125@amdcad.AMD.COM>, phil@amdcad.AMD.COM (Phil Ngai) writes:
>                                            (I won't post that Brian
> does his simulations on an IBM-PC to avoid embarassing him.)

Lemme guess -- using Lotus 1-2-3?

MIPS actually used a neat technique for simulation before they had
hardware.  They wrote an object code converter that turned each MIPS
instruction into one or a few Vax instructions.  You could then just
run the Vax object file and it would run at close to real speeds.
There were also ways to instrument it for instruction counting, cache
simulation, etc.  (Maybe just translate each MIPS instruction into an
increment-a-counter Vax instruction followed by the real translation?)
For debugging the compilers they had a debugger that knew both the MIPS
instructions and the Vax instructions and would keep track of where the
PC was in the simulated MIPS machine, etc.  I thought this was a great
idea.  More info is in the COMPCON '86 paper "Engineering a RISC
compiler system", pg. 136.
-- 
Copyright 1987 John Gilmore; you can redistribute only if your recipients can.
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