jkubicky@nntp-server.caltech.edu (Joseph J. Kubicky) (06/02/91)
(I typed this article up to respond to a query on another mail system I have an account on, but when I tried to post it, the thing choked, so I guess I might as well put it here...) Here's what I know about the Touchstone Delta. I went to the dedication the other day (a big deal - congressmen & other big-shots) and got a good look at the thing. It's impressive - here's some of the stuff off the brochure they were passing out: - 520 numeric nodes w/i860's & 16MB each - 32 disk I/O nodes each w/one 1.4 GB disk (will double each node disk space in July '91). These nodes are 8MB i386's. - 2 tape I/O nodes - 2 netword nodes (Ethernet) i386, 8MB each - 6 service nodes - i386, 8MB - 2 High Performance Parallel Interfaces (HIPPI), each w/ i860 + 32MB mem Peak speed: 31.7 gigaflops (64-bit), 42.2 GFLOPS (32-bit), 17,000 MIPS Total mem: 8.4 GB On-line disk cap: 45 GB (increase to 90 GB in July) External I/O: HIPPI 800Mbit/sec (Oct. '91) Architechture: 2-D 16x36 mesh Internode comm latency: 75-150 ns Bandwidth: 25 Megabytes/sec Sys dimensions: 16ft long, 5 ft high, 3 ft deep Cooling: Air cooled (air blows up through machine from underneath) Power: under 25KW I know a little bit more about the architecture, since I just finished a course taught by the guy who specified it & designed the routing chips (Chuck Seitz). Basically, each node talks to a router chip and all the routers talk to one another. The inter-router communication is asynchronous, meaning that the routers use handshaking instead of clocks. It also means that they run as fast as the technology allows - because there are no clocks, the only limitation on the transfer rate between nodes is the speed of the chips. What they actually get is about 200Mbits (or 25 Mbyte/s, as the sheet said). We spent the last one and a half terms in class designing chips that operate in a computer designed with these routers. Basically, what Seitz would like to see is machines built entirely of 2-D meshes of these routers - thus defining a common inter-chip communication mechanism. The actual routing circuitry is so small that it allows most (>95%) of the area of the chip for other things such as microprocessors and interface chips. In the case of the Delta, they must have used slightly different chips that bring the data wires outside to the i860 nodes (each node is on a roughly 8-by-10 inch board) - in the case of the chips we were building, these data leads were left inside the chip as that's where the processing stuff went. There's a simple protocol associated with the mesh - basically you adress the node you're sending your message to by an X & a Y offset. The routers route all the way in one direction and then all the way in the other (I'm not sure whether X or Y is first). They built the machine with an actual 36x16 grid of LEDs on the front and with big LED bar segments in between, so it's real neat to look at (I imagine there's a switch inside that kills the front panel or the operators will probably go nuts). Anyway, I talked to a guy from Intel about the i860. You might have heard that there are big problems with the memory bandwidth of this thing (if you don't believe it, just take a look at the data book). Anyway, he assured me that the 80860 was just the FIRST in a new family of chips, later versions of which would address these problems. He wouldn't say, however, whether or not these new chips would be drop-in replacements for the old ones. He also assured me that the Delta REALLY WAS getting the kind of performance they said it was (he said they were actually getting 30GFLOPS on some algorithms). Hard to get any straight answers out of him, though - he just kept saying "Stay tuned..." (I wish I could've snagged one of those "Now the Fastest" buttons they were wearing, though... or maybe a section of the "Touchstone Delta Dedication" ribbon that they had sectioning off the rest of the computer room...) Jay Kubicky jkubicky@cobalt.cco.caltech.edu