[comp.arch] AM29000 Memory System??

rajiv@im4u.UUCP (Rajiv N. Patel) (05/07/87)

I have been following the Am29000 discussion since it started.
I was also fortunate to listen to two AMD engineers who were on our
campus yesterday. I do believe that it is a good architecture and
is capable of high performance but I feel that all the performance gains
they(AMD) claim, can only be achieved by using the rather complicated bus
protocols.
By this I mean that the memory system design for the bus interface has to be
done with great care if the sustained performance quoted by AMD is to be
achieved.They use one address bus for two seperate data buses (instr and data)
this means that if burst mode operation is not available the whole concept of
a three bus architecture collapses (ie. as good as a two bus architecture.) .
The pipelined mode for the bus is still more difficult to implement, though 
absense of this feature may affect the performance to a lesser extent.
As a company manufacturing high performance processors I seem to agree that
such features are essential to obtain a good performance but I suppose it would
be nice to see AMD ( or some other vendors) also coming up with a memory system 
suitable for the 29000 to demonstrate their performance claims.
One of the applications mentioned for the 29000 was in high performance 
controller designs, well I would feel that a controller designer would like to
develop his system based on some standard Development Boards (eg. 68K and x86
microprocessor development systems) rather than design the hardware around the
29000 especially the memory system himself.
I suppose all this aspects would already have been thought by the designers
and I would be glad to hear there comments regarding this issue. Recently Tim
Olson did post an article regarding the memory and mentioned about Video RAMS,
I have no much knowledge as to how they work and so am unable to comment on 
that issue. But still how about a complete memory design with all the goodies
the 29000 has to offer. Has something already been developed? I bet this
question would be more suitable for the Sales people rather than the architects
who seem to have done a good work as far as the processor is concerned.



Rajiv N. Patel.

ARPA: rajiv@im4u.utexas.edu
UUCP: {seismo,ucbvax,ihnp4}!ut-sally!im4u!rajiv