poulton@hpl-opus.HP.COM (Ken Poulton) (03/11/89)
> Failing that, are there any other > similarly sized chips that have made it out of the lab? Sure. In *1982*, HP presented (at ISSCC) a 32bit CPU with 450K transistors. It was fabbed in a 1.3um NMOS process. Yield was microscopic at the time of the paper, but soon came up to quite good levels. It was the CPU for the HP 9000 series 500, which I think we still sell. Ken Poulton poulton@hplabs
henry@utzoo.uucp (Henry Spencer) (03/14/89)
In article <62230001@hpl-opus.HP.COM> poulton@hpl-opus.HP.COM (Ken Poulton) writes: >... In *1982*, HP presented (at ISSCC) a 32bit CPU with >450K transistors. It was fabbed in a 1.3um NMOS process. Yield was >microscopic at the time of the paper, but soon came up... I seem to recall a non-HP assessment somewhere which said something like: "The difficulty of getting good results from this self-aligning process is demonstrated by the fact that it hasn't been used for anything else since." -- Welcome to Mars! Your | Henry Spencer at U of Toronto Zoology passport and visa, comrade? | uunet!attcan!utzoo!henry henry@zoo.toronto.edu
baum@Apple.COM (Allen J. Baum) (03/14/89)
[] >In article <62230001@hpl-opus.HP.COM> poulton@hpl-opus.HP.COM (Ken Poulton) writes: >> Failing that, are there any other >> similarly sized chips that have made it out of the lab? > >Sure. In *1982*, HP presented (at ISSCC) a 32bit CPU with >450K transistors. It was fabbed in a 1.3um NMOS process. Yield was >microscopic at the time of the paper, but soon came up to quite >good levels. It was the CPU for the HP 9000 series 500, which >I think we still sell. > >Ken Poulton >poulton@hplabs This is (probably unknowingly) a slight exaggeration. The HP "Focus" chip had 450K transistor SITES. Since this was a microprogrammed machine, many of the sites were in the ROM, where (roughly) half were used. The number of transistors was less than 450K. Still, it was a fair achievement. -- baum@apple.com (408)974-3385 {decwrl,hplabs}!amdahl!apple!baum
loving@lanai.cs.ucla.edu (Mike Loving) (03/14/89)
In article <62230001@hpl-opus.HP.COM> poulton@hpl-opus.HP.COM (Ken Poulton) writes: >> Failing that, are there any other >> similarly sized chips that have made it out of the lab? > >Sure. In *1982*, HP presented (at ISSCC) a 32bit CPU with >450K transistors. It was fabbed in a 1.3um NMOS process. Yield was >microscopic at the time of the paper, but soon came up to quite >good levels. It was the CPU for the HP 9000 series 500, which >I think we still sell. > > >Ken Poulton >poulton@hplabs Two things to be said about this: a) there were 9k words of 38 bit microcode on the chip - thus there were about 360 k fets in ucode. b) 1.3u process? the minimum feature size was 1u the minimum drawn channel length was a little bit more. ------------------------------------------------------------------------------- Mike Loving loving@lanai.cs.ucla.edu . . . {hplabs,ucbvax,uunet}!cs.ucla.edu!loving -------------------------------------------------------------------------------
loving@lanai.cs.ucla.edu (Mike Loving) (03/14/89)
In article <1989Mar13.165931.22528@utzoo.uucp> henry@utzoo.uucp (Henry Spencer) writes: >In article <62230001@hpl-opus.HP.COM> poulton@hpl-opus.HP.COM (Ken Poulton) writes: >>... In *1982*, HP presented (at ISSCC) a 32bit CPU with >>450K transistors. It was fabbed in a 1.3um NMOS process. Yield was >>microscopic at the time of the paper, but soon came up... > >I seem to recall a non-HP assessment somewhere which said something like: >"The difficulty of getting good results from this self-aligning process >is demonstrated by the fact that it hasn't been used for anything else >since." >-- au contraire the exact same process was used for fabbing 4 or 5 other chips in that same machine and a slightly improved version of it was/is used to fabricate the chips for Spectrum (HP Precision Architecture - RISC) ------------------------------------------------------------------------------- Mike Loving loving@lanai.cs.ucla.edu . . . {hplabs,ucbvax,uunet}!cs.ucla.edu!loving -------------------------------------------------------------------------------
pavlov@hscfvax.harvard.edu (G.Pavlov) (03/14/89)
In article <1989Mar13.165931.22528@utzoo.uucp>, henry@utzoo.uucp (Henry Spencer) writes: > In article <62230001@hpl-opus.HP.COM> poulton@hpl-opus.HP.COM (Ken Poulton) writes: > >... In *1982*, HP presented (at ISSCC) a 32bit CPU with > >450K transistors. It was fabbed in a 1.3um NMOS process. Yield was > >microscopic at the time of the paper, but soon came up... > > I seem to recall a non-HP assessment somewhere which said something like: > "The difficulty of getting good results from this self-aligning process > is demonstrated by the fact that it hasn't been used for anything else > since." > -- Well, granted that it was nowhere near 450k's worth of cpu. But the HP9000/ 500 did use several other chips (i/o processor, for one) that were in the same architectural family and using the same process. And a similar process was applied to the Spectrum (at least the first generation). greg pavlov, fstrf, amherst, ny
ron@motmpl.UUCP (Ron Widell) (03/16/89)
In article <7392@polya.Stanford.EDU> maslen@polya.Stanford.EDU (Thomas Maslen) writes: >I *think* this is comp.arch material... >I got into a lively discussion last night with a couple of people who claimed >that nobody in the US could fabricate a chip like the N-10 (excuse me, i860; >did I get it right?) with any useful sort of a yield. As supporting evidence >they mentioned (first I'd heard of it) that Motorola had been unpleasantly >surprised by the difficulty of producing fully working 88K chips, which is a > - don't spill your company secrets to me or the net (of course). > Thomas Maslen maslen@polya.stanford.edu That sort of transistor count has been available on a single chip (at least as a lab curiosity) since roughly 1980. The problem back then was packaging (device geometries being what they were, the chips were *BIG*). Today, such densities are eminently doable (you might say we're betting the company on it :^)). The 88k problems were not due to chip density, but to the fact that we were trying to debug two (inter-related) things at once. Remember, the 88k was not a hand-packed design, but the output of a silicon compiler; so we had to debug both the definitions going into the compiler as well as the compiler itself. (Can you say "Chase your tail"? :^)). -- Ron Widell, Field Applications Eng. |UUCP: {...}mcdchg!motmpl!ron Motorola Semiconductor Products, Inc., |Voice:(612)941-6800 9600 W. 76th St., Suite G | I'm from Silicon Tundra, Eden Prairie, Mn. 55344 -3718 | what could I know?
davidsen@steinmetz.ge.com (Wm. E. Davidsen Jr) (03/21/89)
In article <1161@motmpl.UUCP> ron@motmpl.UUCP (Ron Widell) writes: | The 88k problems were not due to chip density, but to the fact that we were | trying to debug two (inter-related) things at once. Remember, the 88k was | not a hand-packed design, but the output of a silicon compiler; so we | had to debug both the definitions going into the compiler as well as the | compiler itself. (Can you say "Chase your tail"? :^)). A silicon compiler in theory will let you change processes by simply putting in the design rules for the new process and recompiling the chip. I've seen some claims of this, but the processes were all low tech. Could you comment on the ability of your compiler to do that, if someone needed the 88k in something new, like 7000 angstrom radiation hard boron phosphate (just an example)? I realize that this may be (probably is) proprietary. but I thought I'd ask. -- bill davidsen (wedu@crd.GE.COM) {uunet | philabs}!steinmetz!crdos1!davidsen "Stupidity, like virtue, is its own reward" -me