jk3k+@andrew.cmu.edu (Joseph G. Keane) (02/03/88)
I've heard of a `super multiplier', a big gate-array which multiplies without any clocking. I assume this was only integer multiplies, though. Does anyone know if this has been done for floating point? What are the fastest times (ns) that have been done for various multiplies? --Joe
tim@amdcad.AMD.COM (Tim Olson) (02/04/88)
In article <oW1nb5y00Xo74Lw0F3@andrew.cmu.edu> jk3k+@andrew.cmu.edu (Joseph G. Keane) writes: | I've heard of a `super multiplier', a big gate-array which multiplies without | any clocking. I assume this was only integer multiplies, though. Does anyone | know if this has been done for floating point? What are the fastest times | (ns) that have been done for various multiplies? The Am29325 from Advanced Micro Devices is a custom bipolar floating-point processor (single-precision) which is purely combinatorial (no clocking, except for the status register). It can add, subtract, multiply, or convert in 125ns. About 30% of the chip area is devoted to the multiplier array. The Am29027 is a new, double-precision CMOS floating-point processor, which can be pipelined or not. In flow-through mode, it can multiply two double-precision IEEE values in 250ns, or 125ns pipelined. It has a full 52 bit x 52 bit multiplier on chip (BIG!) -- Tim Olson Advanced Micro Devices (tim@amdcad.amd.com)
hansen@mips.COM (Craig Hansen) (02/04/88)
In article <oW1nb5y00Xo74Lw0F3@andrew.cmu.edu>, jk3k+@andrew.cmu.edu (Joseph G. Keane) writes: > I've heard of a `super multiplier', a big gate-array which multiplies without > any clocking. I assume this was only integer multiplies, though. Does anyone > know if this has been done for floating point? What are the fastest times > (ns) that have been done for various multiplies? Integer multipliers in 16x16 & 32x32 sizes have been around as commercial products (usually not in gate arrays) for a while, from TRW (developed market with a burning hot bipolar chip), Weitek (first nMOS replacement part), AMD, IDT, ADI, and many others. Floating-point multipliers (and adder/subtractors) without internal latches in the computation path also exist; Weitek first introduced some fully-pipelined 32-bit parts in nMOS and later in 64-bit and CMOS, that could operate with the pipeline latches disabled (flow-through mode). IDT, AMD, ADI also have competitive parts, and BIT has a set of parts in ECL-VLSI. The fastest? Does anyone beat BIT, at 35 ns for IEEE single, 45 ns for IEEE double multiplies? This is from a preliminary data sheet, and doesn't include on-chip and off-chip delays. Disclaimer: I hold stock in some of these companies, no matter how unprofitably. -- Craig Hansen Manager, Architecture Development MIPS Computer Systems, Inc. ...{ames,decwrl,prls}!mips!hansen or hansen@mips.com 408-991-0234
beyer@houxs.UUCP (J.BEYER) (02/05/88)
If memory serves, the NORC (Naval Ordinance Research Computer) by I.B.M., had an "instantaneous" multiplier. That was in vacuum-tube days. I think the machine had over 10 decimal digits fraction and 2 decimal digits exponent. As I recall, it did a floating point add and a floating point multiply in the same amount of time.