moore%cdr.utah.edu@cs.utah.edu (Tim Moore) (03/15/90)
On the MIPS R2000 and R3000 processors, does the following instruction
have predictable results?
lw $1,some_disp($1)
$1 is also $at and is used internally by the MIPS assembler, but I'm
not using the MIPS assembler.
Thanks,
Tim Moore moore@cs.utah.edu {bellcore,hplabs}!utah-cs!moore
"Ah, youth. Ah, statute of limitations."
-John Waterstarolli@riva.esd.sgi.com (Gary Tarolli) (03/16/90)
In article <1990Mar14.165530.17748@hellgate.utah.edu>, moore%cdr.utah.edu@cs.utah.edu (Tim Moore) writes: > On the MIPS R2000 and R3000 processors, does the following instruction > have predictable results? > > lw $1,some_disp($1) > > $1 is also $at and is used internally by the MIPS assembler, but I'm > not using the MIPS assembler. Yes, it is predicatable - two cycles later $1 will contain the data located at some_disp($1). Note $1 cannot be used in the cycle immediately following the lw instruction, however other instructions including lw can be done there. If you were using the assembler, you could use .set noat to tell the assembler not to use $at. If you are not using the assembler, then I assume you are generating object code yourself. If you are doing this while the program is running then don't forget to flush the icache. In either case, you must respect the load delay of 1 cycle. -- Gary Tarolli
jwag@moose.sgi.com (Chris Wagner) (03/16/90)
In article <1990Mar14.165530.17748@hellgate.utah.edu>, moore%cdr.utah.edu@cs.utah.edu (Tim Moore) writes: > On the MIPS R2000 and R3000 processors, does the following instruction > have predictable results? > > lw $1,some_disp($1) > > $1 is also $at and is used internally by the MIPS assembler, but I'm > not using the MIPS assembler. > Thanks, > > Tim Moore moore@cs.utah.edu {bellcore,hplabs}!utah-cs!moore > "Ah, youth. Ah, statute of limitations." > -John Waters No problem, this is just fine (if your your doing your own pipeline scheduling remember to wait once instruction before accessing AT). Chris Wagner
mitch@rock.sgi.com (Tom Mitchell) (03/21/90)
In article <53751@sgi.sgi.com> tarolli@riva.esd.sgi.com (Gary Tarolli) writes: * In article <1990Mar14.165530.17748@hellgate.utah.edu>, moore%cdr.utah.edu@cs.utah.edu (Tim Moore) writes: * > On the MIPS R2000 and R3000 processors, does the following instruction Good stuff in previous notes. * -- * Gary Tarolli Thanks Gary, Let me ADD to this note. Since it took me too long to find this reference. I'll share: "mips RISC Architecture" by Gerry Kane (Integrated Device Technology) (c) 1988 Mips Computer Systems Prentice Hall, Englewood Cliffs, N.J. ISBN 0-13-584293-x I picked up my copy from a local 'computer' literate bookstore. While it is rare to use assembler with MIPS/SGI compilers.... There are those times. Thomas P. Mitchell -- mitch@sgi.com "All things in moderation; including Grammarians."