[comp.arch] ETA?

lm@cottage.UUCP (06/05/87)

Hi.  Does anyone out there know about the ETA machine?  It's supposed
to be a supercomputer made by a spinoff from CDC.   What can you tell
me about this machine?   Will it run normal applications?  What's the
memory management look like?  Etc.   I'm interested in information from
an OS point of view.

Thanks in advance.


Larry McVoy 	        lm@cottage.wisc.edu  or  uwvax!mcvoy

rchrd@well.UUCP (06/05/87)

The ETA-10 is (will be? was? might be?) an 8 processor system.
Each processor is essentially a Cyber-205.
This means that each processor has a scalar and a vector
processor. THe scalar processor is a 200 mips machine with
a 64 word instruction stack, and a 256 word (64 bit) register
file, with independent segmented functional units.
The CPU memory is 64k mos sram, 4 million 64 bit words.
It is secded for each 32 bits with 75 billion bit/sec 
bandwidth.  It is a virtual memory system (just like the 205).
There is also a shared memory with 256k mos dram, 65 to 256
million words secded, 8 cpu ports at 12 billion bit/sec 
bandwidth per port.
  
Apparently, there will also be a 4 processor version.
  
CPU Clock cycle is supposed to be 5 to 9 nanoseconds.
  
Like the cyber-205, it will have all the problems of that
machine.  CDC has a very arrogant attitude towards programming,
and to attain the top speed of the machine, you have to
write in 205-FORTRAN with many non-standard syntax constructs.

Unlike the CRAY and other vector processors, the 205 is a memory to
memory pipeline, and can only attain high speeds for long 
vector lengths.  Virtual memory also degrades vector performance
everytime there is a reference out of in-core memory. 
  
Still, the ETA-10 is not a real machine, with no real working
systems in place.  It is also perhaps significant that rumor
has it that CDC has pulled out some of its staff on loan to
ETA.
  
Time will tell... ETA is going to have a hard time selling this
machine.

-- 
...Richard Friedman [rchrd]  Pacific-Sierra Research
2855 Telegraph #415, Berkeley CA 94705  415 540 5216
uucp:  {ucbvax,lll-lcc,ptsfa,hplabs}!well!rchrd
- or -   rchrd@well.uucp

baum@apple.UUCP (06/08/87)

--------
[]
>In article <3238@well.UUCP> rchrd@well.UUCP (Richard Friedman) writes:
>Still, the ETA-10 is not a real machine, with no real working
>systems in place.

Do you know something we don't? ETA claims to have delivered a working machine
to U. of Florida.

--
{decwrl,hplabs,ihnp4}!nsc!apple!baum		(408)973-3385

grunwald@uiucdcsm.UUCP (06/10/87)

I think that the ETA systems are cyber-205 work-alikes. THe ETA-10 is a
box containing 10 of the CPUS. I haven't heard much about the memory
heirarchy (if any) or the performance.

utterback@husc4.UUCP (06/11/87)

In article <3300007@uiucdcsm> grunwald@uiucdcsm.cs.uiuc.edu writes:
>
>I think that the ETA systems are cyber-205 work-alikes. THe ETA-10 is a
>box containing 10 of the CPUS. I haven't heard much about the memory
>heirarchy (if any) or the performance.

The ETA-10 Can have from 1 to 8 CPUs.  Since there has been so much interest
recently, I will give some facts(?) that I know about the ETA-10.  This is 
from a product presentation that they gave, and I am working for the 
competition, so take everything with a grain of salt. 8-)

1st system to FSU
2nd system to Princten, JVNC.

240 Chips on each PC board (16"x22")
Each chip os 1 cm2
Each CPU holds 4MW of local memory
Memory is air-cooled.
CMOS Gate Arry [ALSI - 20k]
Cyber-205 instruction compatibility.
Factor of 10 improvment over 205 on short vectors.
G Series is Liquid Nitorgen cooled, 45 Minutes to cool down, 90 Minutes to 
  warm back up.
7 ns clock with Liq. N.  14ns clock in air.

OPTIONS:
2,4,6,8 CPUs with 4MW memory each
64, 128, 192, 256 MW Shared Memory
2 to 18 I/O Units
Optional Redunancy on 2 and 4 processors.
Redundancy standard on 6 and 8 processors.

Memory:
  Local:
    64K MOS SRAM
    SECDED for each 32 bits
    75 billion bits/sec bandwidth
    virtually addressed.
  Shared:
    256K MOS DRAM
    32-256 MW with SECDED
    8 hi-speed cpu ports 
    18 lo-speed ports

O.K., there it is.  Like I said, this was from a marketing product presentation,
so I can't vouch for the accuracy of the claims.  Also, don't ask me for more 
details, I don't have them, and I don't even understand all that I wrote above.

Brian Utterback
>Everything in this message is the opinion of myself and not my employer. <
>I am representing only myself, and if you can, forget that you saw my    <
>name on it, O.K.?

eugene@pioneer.arpa (Eugene Miya N.) (06/11/87)

Brian-- (and others)
Since you noted you work for the "competition."
Just a word of note: Neil Lincoln, the chief architect of the 10 does
read this news group (although he tells me that he spends more time on
his Amiga reading comp.*amiga [interesting contrast Cray builts Crays on
Apples, Neil builds ETAs on Amiga, (will Commodore buy an ETA?) think
of those lines .....;-)]).  Seymour does not read news, but I heard
he gave a chuckle when people (like Patterson) started crediting him
with RISCs.

From the Rock of Ages Home for Retired Hackers:

--eugene miya
  NASA Ames Research Center
  eugene@ames-aurora.ARPA
  "You trust the `reply' command with all those different mailers out there?"
  {hplabs,hao,ihnp4,decwrl,allegra,tektronix,menlo70}!ames!aurora!eugene

trb@stag.UUCP ( Todd Burkey ) (06/12/87)

Slight Correction...Neil Lincoln uses Atari ST's, not Amigas...But he
laughed when he saw the message...

  -Todd Burkey (YAAA-Yet Another Atari Addict)
  ..ihnp4!meccts!stag!trb