lamaster@ames.arc.nasa.gov (Hugh LaMaster) (03/21/89)
The subject of "How fast is the i860?" reminds me of something I just saw in the IEEE magazine "The Institute". The page 1 article of the April 89 issue, "Computing at 100 MIPS" states that with superfast micros coming, 100 MIPS (whatever they are) may be coming. The article then describes a panel held at the IEEE Solid-State Circuits Conference, Feb. 15. I now quote: : : (various ideas) : "The panel also spent considerable time dispatching notions they felt would not lead to a successful 100-MIPS microprocessor. One of these was the so-called very long instruction word architecture, in which..." I don't know if this summary was accurate, but, assuming it was, I was surprised to see such a blanket dismissal. But, it reminds me: Using some reasonable standard benchmarks, such as those used in the MIPS Performance Brief, how do the Multiflow machines stack up? If they were assigned VUPS-ratings, how many VUPS do they achieve using the harmonic mean of those benchmarks? And, more interestingly for this group, how efficiently are loops executed on a per-cycle basis relative to other machines: what I mean is, on some simple loops, how many instruction cycles are required, relative to the number of instruction cycles on, say, a VAX? Another interesting number would be: how many memory references are generated on the Multiflow, which doesn't try to minimize memory accesses per se, relative to a VAX? Is this number "large", and is that why this architecture was dismissed for the purpose of cheap (bus based) micros? Hugh LaMaster, m/s 233-9, UUCP ames!lamaster NASA Ames Research Center ARPA lamaster@ames.arc.nasa.gov Moffett Field, CA 94035 Phone: (415)694-6117