picano@en.ecn.purdue.edu (Silvio Picano) (04/13/91)
Does anyone know how many outstanding (i.e., buffered) load & store instructions the i860 is capable of at a given moment? Also, how is this really implemented? Is it as simple as I imagine (just placing a 'pending' notice on the dest register and forward the request-info to a special fetch buffer controller, which will cycle steal on the bus)? The processor will continue until an interlock occurs for this register value. I only have a prelim data sheet on the i860 (Oct 89), which does not get into sig. detail on the above. Thanks Silvio picano@ecn.purdue.edu