news@usc.edu (09/16/90)
Has anyone set up a RISC architecture where you can supply branch logic as a vector (e.g. an ordered set of ordered pairs along the lines of substitute "this address" for "that address")? [I use a variation on this in my own work as a way of implementing time-critical loops, and I've seen it in some HLL's]
news@usc.edu (09/17/90)
In article <11991@chaph.usc.edu> I wrote:
Has anyone set up a RISC architecture where you can supply branch
logic as a vector (e.g. an ordered set of ordered pairs along the
lines of substitute "this address" for "that address")?
um.. the more I think about how I use this, and the more I think about
considerations such as nesting/function calls/restartability, the more
I think no-one would use ordered pairs. A more appropriate mechanism
(e.g. what I use) is set up the vector, and have an instruction which
fetches the next element and does the branch.
I guess the point I was trying to make is there is a way of removing
branch penalties from deep pipelines. Presuming you can feed this
information into the prefetch mechanism adequately.
That, and I want to know if any hardware already supports this idea to
any extent.