RWilson@acorn.co.uk (05/11/89)
In the previous article jhallen@wpi.wpi.edu (Joseph H Allen) writes: >Speaking of warped semaphores, a nifty test-and-set instruction can be made on >machines (like 6809 where I originally used it) which have rotate memory: > >Lock a resource: > >wait: ror lock > bcc wait The ARM2 (VL86C010) semaphore is considerably more warped than this "standard practise" on 6800, 6809, 6502 etc processors. Basically it involves the indivisibility of the LDM, STM (load multiple, store multiple) instructions to alter blocks of data==instructions to provide a semaphore. About 40 ticks to test and set the semaphore: for light weight multitasking this seemed much too expensive, so we added SWAP memory and register to ARM3. >On a different note, how difficult is offset optomizations for machines (like >the ARM and most other RISC processors, I think) with offsets which are >smaller than the address space? This is a simple matter for compilers, but doesn't seem to generate any pain for assembler programmers, either. Most RISC processors have two restrictions: size of immediate value for data processing and size of offset for address calculation. Breaking these down into multiple steps is quite simple. >With the ARM, I notice that the lower 2 address bits are output. Could these >be used to interrupt the processor for handling misaligned words? Yes, you could use these externally for misaligned words, either generating an exception or doing two memory cycles. However, most of our programs actually use the processor's handling of misaligned words (move the word rotated such that the addressed byte is in the lsb of the register) to implement both misaligned word transfer and partial word load (e.g. half word load). In particular, the C compiler does this..... >(yes, I did just get ARM chip info and I'm thinking of doing something neat >with this $45 dollor 32 bit chip- I also see that VLSI is planning to make >20Mhz and 32Mhz versions... a 32Mhz version would faster than SPARC...) Note that ARM3 (VL86C020) is the one on the smallest technology and hence advertised to go very fast: ARM2 may get there eventually (and will need fast memory to support it). ARM3 is $199 for samples, $100 for quantity. Roger Wilson (RWilson@acorn.co.uk)