bcase@amdcad.UUCP (Brian Case) (03/16/87)
Some of you noticed my "Watch this space" comment at the bottom of
several of my recent postings about large register files and stack
caches. Well, this is what I was talking about: The Am29000. This
is a high-performance CMOS microprocessor with a very larger register
file. Part of the register file (128 of the registers) can be used
as a stack cache.
The formal annoucement of the chip is today in San Francisco, so we
are finally free to talk about it. If you have questions, you can
send mail to me or Tim Olson (amdcad!tim). I am one of the original
designers, Tim joined to project later.
Some features: 25 MHz clock (40 ns cycle time); nearly all instructions
single cycle; 192, 32-bit, fully general-purpose registers; 64-entry,
two-set associative TLB with software reload; 128-instruction branch
target cache (32 four instruction entries); load/store architecture;
three-address architecture; delayed branches; overlapped loads and
stores; register protection in banks of 16 registers; 128 "local"
registers addressed relative to an internal "stack pointer;" 25 MIPS
max., 17 MIPS sustained running big programs (like nroff, our own
Am29000 assembler); 21621 dhrystones (using the C compiler that I
wrote (i.e., not the best, not the worst) and our low-level simulator
assuming 64KByte data and 64KByte instruction caches each with two-
cycle first access and single-cycle burst (i.e. each subsequent,
sequential) access) for version 1.1 Dhrystone (the number does not
change much for smaller caches). Note: The chip does not require
caches to run fast in embedded applications.
This is not meant to be an advertisement. I think it is safe to
assume that there will be interest in this chip; I just want to let
you guys know that we are here and able to answer your questions.
Brian Case
Tim Olson
Smeeta Gupta