stuart@cs.rochester.edu (Stuart Friedberg) (02/24/88)
In article <1370@vaxb.calgary.UUCP>, radford@calgary.UUCP (Radford Neal) writes: > Several instruction sets, such as the 68020 and the VAX, have > an "indexed" addressing mode, in which a register is shifted > left by 0, 1, 2, or 3 bits before being added to a displacement, > allowing easy access to arrays of ints, etc. The BLIZZARD design may be of interest in this context. It supports data operands of 1, 2, 4, 8, 16, and 32 BITS in length, in contrast to VAX et alia that support data of 1, 2, 4, and 8 BYTES in length. However, there is no load address instruction and therefore no access to the kind of auto-shift arithmetic Neal discusses in his article. Ronald L. Rivest The BLIZZARD Computer Architecture Computer Architecture News, 7, 9 (15 August 1979), pp. 2-10 Stu Friedberg {ames,cmcl2,rutgers}!rochester!stuart stuart@cs.rochester.edu