earle@jplopto.uucp (Greg Earle) (08/18/87)
I just saw a new book devoted to RISC architectures. Sorry to be so sketchy, but I didn't catch the author's name or the exact title (but it was something simple like `RISC Architectures' or similar). It had sections on most of the known research and commercial RISC processors. The only ones missing were the MIPS chipset (covered somewhat by an entry for the Stanford MIPS project?) and the Sun-4/SPARC/SunRise project (obviously too new, although the book is copyright 1987). I think the author was from U. of Texas, but don't quote me. Anyone provide more information, and possibly a review? Worth buying? Greg Earle earle@jplopto.JPL.NASA.GOV (formerly of) JPL earle%jplopto@jpl-elroy.ARPA [aka:] (currently gainfully earle%jplopto@elroy.JPL.NASA.GOV unemployed) ...!cit-vax!elroy!smeagol!jplopto!earle