hermann@cpsc.ucalgary.ca (Michael Hermann) (11/08/88)
High Performance Mathematical Sieve
Myself and another grad student at the University of
Calgary have designed a high performance mathematical sieve.
In order to get it built we'll have to sell some of them to
pay for development costs, and so we're looking for some
feedback from netters out there to see how likely they'd be
to sell.
In the context of mathematics, sieving is an algorithm
used to solve sets of linear congruences. It is useful in
the following situations:
o finding a set of consecutive prime numbers.
o solving Diophantine equations (ie. finding integer
solutions to multivariate polynomials)
o some factoring algorithms.
We think that our system will be useful to researchers
in number theory, cryptography and computer science, by pro-
viding millions of (specialized) operations per second at a
low cost, relative to using software methods on general pur-
pose computers.
The design is an evolution of the D. H. Lehmer sieves
which takes advantage of current technology, and has the
following features:
o standalone design includes 2 RS232C interfaces (for
connection to a host computer and user terminal) and
internal power supply.
o simple user/host interfaces.
o built in monitor firmware handles almost all functions
of the sieve and interface.
o portable to any host machine supporting UNIX (tm AT&T)
and the 'C' language (bundled 'C' software included)
o 50 nSEC cycle time hardware.
o single board construction consists of:
1) Generic 16-bit microprocessor.
2) 16K ROM (holds monitor firmware)
3) 16K scratchpad RAM
4) 2 Application Specific Integrated Circuits
(ASIC's).
5) 15 expansion sockets for additional ASIC chips.
o one of the ASIC's is a Sieve Engine Chip, which con-
tains 32 hardware "rings", or recirculating shift
registers, and first level solution detection logic
for the sieve.
o the other ASIC is a Sieve Control Chip, which handles
all internal control logic, and orchestrates the oper-
ation of the Sieve Engine chips on the board.
o additional rings are emulated by the monitor software
running on the microprocessor, with no speed degra-
dation.
PERFORMANCE:
Initial board configuration with single Sieve
Engine chip:
160 million trials per second (MTS).
SCALABILITY:
System is scalable in 160 MTS increments by adding
sieve engine chips to board (upto a maximum 16). This will
give a fully configured peak performance of a little over
2.5 billion trials per second.
We're trying to have the cost of the fully configured
system be something less than $5000 (Cdn.) in cost, and have
it available by early 1990. It will take a while to put this
together, as we're working on our degrees and can only put
about 10% of our time into this project.
Right now we're negotiating with a local company to
invest the fabrication costs, and they require current
market information. What we'd like you to do is tell us if
you'd be interested in buying our box if it gets built, and
what you'd be doing with it (ie. are there any applications
we haven't mentioned?). We'd also be more than happy to
answer any further questions anyone might have. Hopefully,
this will also generate some interesting conversation in the
newgroups.
If you know of anyone else who may be interested, but
was not able to read this net posting, we'd appreciate you
passing this information along to them as well.
Thankyou for your time.
Mail:
Mike Hermann
c/o Computer Science Dept.
University of Calgary
2500 - University Drive NW
Calgary, Alberta, CANADA
T2N - 1N4
UseNet: ..uunet!ubc-cs!calgary!hermann
Arpa : calgary!hermann@cs.ubc.ca
Ean : hermann@cpsc.calgary.cdn
Voice : (403) 2207691 (messages 2301224)cme@cloud9.UUCP (Carl Ellison) (11/10/88)
In article <179@cs-spool.calgary.UUCP>, hermann@cpsc.ucalgary.ca (Michael Hermann) writes: > > [ bulk of advertisement deleted ] > > PERFORMANCE: > Initial board configuration with single Sieve > Engine chip: > 160 million trials per second (MTS). OK -- I'll bite --- What's a trial? Is this a trial division ? Is it an addition -- and if so, how many hundreds of decimal digits? --Carl Ellison ...!harvard!anvil!es!cme (normal mail address) ...!ulowell!cloud9!cme (usenet news reading) (standard disclaimer)
castillo@mit-amt (Brian C. Anderson) (11/10/88)
In article <179@cs-spool.calgary.UUCP> hermann@cpsc.ucalgary.ca (Michael Hermann) writes: > > High Performance Mathematical Sieve . . . > We're trying to have the cost of the fully configured >system be something less than $5000 (Cdn.) in cost, and have >it available by early 1990... . . . > If you know of anyone else who may be interested, but >was not able to read this net posting, we'd appreciate you >passing this information along to them as well. There is one very well financed organization that might be extremely interested in hardware solution of the type you propose, known in the US as the NSA. They are, however, quite paranoid about security matters. :-)