oconnor@nuke.steinmetz (Dennis M. O'Connor) (08/10/88)
An article by ward@cfa.harvard.EDU (Steve Ward) says: ] In article <>, henry@utzoo.uucp (Henry Spencer) writes: ] > In article <> mcdonald@uxe.cso.uiuc.edu writes: ] > >... in core memories a read destroyed the contents of the cores, ] > >so every read had to be followed by a write)... ] > ] > Dynamic RAMs are the same way, actually, although many people aren't aware ] > of this because the chips hide most of the ugly details. [...] ] ] actually, this is not correct. actually, Henry Spencer is absolutely correct. Obviously, you weren't aware of it because the chips hide the ugly details. :-) ] Dynamic RAM does not have destructive readout. In fact, the DRAM is ] refreshed with a read-only cycle in typical applications. DRAM's do ] have special timing and refresh considerations, though. A write cycle also refreshes one row of the DRAM array. But changes one of the bits. So writes aren't generally used for refresh-only cycles. :-) ] A DRAM is made up of one or more circular, dynamic shift registers with ] read/write/address logic. [...] This is dead wrong. DRAMs are made up of one or more arrays of one-capacitor-one-transistor cells. On a read ( and before a write, as well ), activating a word line cause one row of these cells to turn on their transistors, dumping their charges, DESTRUCTIVELY, onto the sense lines. Whatever else may happen, this data is later-in-the-cycle written back onto the sense lines, with the word line still active, recharging the caps. ( I think on some designs the data is actually INVERTED when re-written, and one bit per word is kept around to keep track of wether the bits are in true or complement form. ) Now bubble memories ARE shift-register based. That's why they have "average latency" specs. Ya gotta wait for the bit to shift around. ] <DON THE ASBESTOS CLOTHING :-) fire away No need for flames, you're just misinformed. DRAMs are not shift-register based storage. Period. ( Now, Video DRAMs do contain a shift register for shifting out a selected word, but it is NOT the primary data storage mechanism. So I digress. ) -- Dennis O'Connor oconnor%sungod@steinmetz.UUCP ARPA: OCONNORDM@ge-crd.arpa "Never confuse USENET with something that matters, like PIZZA."
phil@amdcad.AMD.COM (Phil Ngai) (08/11/88)
In article <11815@steinmetz.ge.com> oconnor%sungod@steinmetz.UUCP writes: >( Now, Video DRAMs do >contain a shift register for shifting out a selected word, >but it is NOT the primary data storage mechanism. So I digress. ) Actually, there are many video DRAMs which implement the so called shift register as a little piece of fast static RAM addressed by a counter. How fast? A Toshibia megabit VRAM accesses in 25 nS. Part of that is the counter working so the RAM itself must be maybe 15-20 nS. With regard to the question of how DRAMs work, Mr Ward is so wrong I can't believe it. But I wonder how the new-fangled "DRAMS" with static column access or extended page mode work. Do they actually discharge the capacitor and write it back with each page access? In 50 nS? -- I speak for myself, not the company. Phil Ngai, {ucbvax,decwrl,allegra}!amdcad!phil or phil@amd.com