mdeale@cosmos.acs.calpoly.edu (Myron Deale) (10/24/89)
I don't have the data sheet on the i960CA yet and wanted to ask a few questions anyway. What is the power dissipation for a 33MHz part? does the CA seem to require a lot of extra chips? The articles I've read have been mildly confusing. Is the inst. cache 1KByte or 1KWord (4KB) ? two-way set assoc w/ a 4-word line? and what of the data side and this "variable" stuff? -Myron // mdeale@cosmos.acs.calpoly.edu
mcg@mipon2.intel.com (Steven McGeady) (10/30/89)
In article <1989Oct24.092403.19585@polyslo.CalPoly.EDU>, mdeale@cosmos.acs.calpoly.edu (Myron Deale) writes: > What is the power dissipation for a 33MHz part? Worst-case power dissipation for the 33Mhz is approximately 2.5W. This is based on ICC(HOT) of 550 mA at nominal 5.0 V. The processor now comes in a 1.78" square ceramic 168-pin package. The 960CA is specified for operation for case temperatures between 0 and 100 degrees C. > does the CA seem to require a lot of extra chips? This you'll have to judge for yourself. However, two companies (Heurikon and Tadpole) have put the CA on a single standard VME bus board (approx. 6x9) along with an 82596 ethernet controller, SCSI, multiple serial ports, and 4-8 Mb of DRAM and the VME interface without any difficulty. The CA hooks up to the 82596CA ethernet chip, and to 27C960 burst eproms with little or no glue, and since the on-chip bus controller allows software settable wait-state generation, bus-width (8, 16, 32), byte sex (little- or big-endian) on a region-by-region basis (16 regions), memory interface is extremeley simple. The external bus is nominally 32-bit demuxed address and data. The chip accepts either a 1x or a 2x external clock. > The articles I've read have been mildly confusing. Is the inst. cache > 1KByte or 1KWord (4KB) ? two-way set assoc w/ a 4-word line? and what > of the data side and this "variable" stuff? The on-chip instruction cache is 1Kb, or 256 one-word instructions long. It is organized as 64 lines of four words each, and is managed as two-way set associative with LRU replacement. The chip does not have a data cache. Rather, it has a 1.5Kb on-chip SRAM array. A programmable portion of this is dedicated to the user's stack-frame (or local register) cache [the area where registers are saved when entering procedures]. The remainder is available to the user for any use other than instruction fetching. The SRAM is mapped into the memory space starting at location 0. Typical uses of the remaining SRAM are for secondary stacks, or as buffer space for critical variables. Bandwidth to and from the on-chip SRAM is 500 Mb/sec, using a 128-bit wide load and store buses. In other words, four registers can be loaded or stored in a single cycle (of latency) using the 'ldq' or 'stq' instructions. This is the same latency as normal register-register moves, effectively giving the user an additional 256 or more registers-speed storage space. S. McGeady Intel Corp.