paul@mozart.amd.com (Paul Schnizlein) (12/04/90)
In article <1990Nov26.205811.27083@zoo.toronto.edu> henry@zoo.toronto.edu (Henry Spencer) writes: > >??? The AMD 29k BTC, the major example that I know about, works regardless >of what kind of branch you use. It even works on interrupts, as I recall. Yes, it also caches targets of traps, and returns from interrupts and traps. That is, it caches the target instruction(s) of every non-sequential fetch. By the way, the Am29000 cache stored 4 instructions at the target of each branch. The new Am29050 cache can be configured by the user to store 4 or 2 instructions. Storing only 2 means more blocks are available in the fixed 1 kbyte storage space. This allows a higher hit rate. With a memory system that can return a first access in 2 wait cycles, this is especially attractive. -- "It's never too late to have a happy childhood" paul@mozart.amd.com (Paul Schnizlein)
ccplumb@spurge.uwaterloo.ca (Colin Plumb) (12/05/90)
>In article <1990Nov26.205811.27083@zoo.toronto.edu> henry@zoo.toronto.edu (Henry Spencer) writes: >> >> ??? The AMD 29k BTC, the major example that I know about, works regardless >> of what kind of branch you use. It even works on interrupts, as I recall. In article <1990Dec3.202239.13188@mozart.amd.com> paul@mozart.amd.com (Paul Schnizlein) writes: > Yes, it also caches targets of traps, and returns from interrupts and > traps. That is, it caches the target instruction(s) of every > non-sequential fetch. It also caches page boundaries. I thought this was really nifty the first time I heard about it, until I realized the simple implementation: basically, when the processor negates the burst request line, it turns on the BTC. -- -Colin