feustel@netcom.UUCP (David Feustel) (12/22/90)
Anyone have any info on this chip? It was announce in yesterday's WSJ but with no details. -- David Feustel, 1930 Curdes Ave, Fort Wayne, IN 46805, (219) 482-9631 EMAIL: netcom.uucp
wolfe@vw.ece.cmu.edu (Andrew Wolfe) (12/28/90)
Apparrently, Intel has submitted a paper to ISSSC describing a 100MHz i486. By ISSSC rules, this requires working silicon. Intel claims that the chip has been produced but that there are NO marketing plans at this time.
feustel@netcom.UUCP (David Feustel) (12/28/90)
Intel almost had a deal set with PRIME to produce a 100 Mhz ECL 486, but it was scuttled by the attempted takeover of PRIME by MAI Basic 4. -- David Feustel, 1930 Curdes Ave, Fort Wayne, IN 46805, (219) 482-9631 EMAIL: netcom.uucp
jjb@sequent.UUCP (Jeff Berkowitz) (12/29/90)
In article <19470@netcom.UUCP> feustel@netcom.UUCP (David Feustel) writes: >Intel almost had a deal set with PRIME to produce a 100 Mhz ECL 486, >but it was scuttled by the attempted takeover of PRIME by MAI Basic 4. With all due respect to the business problems at Prime, I don't think that's the only reason. The Intel ISSCC paper about the 100Mhz CMOS '486 pretty much sums up the situation with ECL CPU implementations. At any point in time during the last few years, it's been possible to build and ECL CPU which is faster than an MOS implementation. But the ECL guys never seem to get one full product generation (24 - 36 months) ahead; it's always more like 12 to 18 months. Taken together with the higher product cost of the ECL implementation, the end result is that the ECL products can never quite justify themselves in the marketplace. This applies equally to RISCs like the MIPS processor, CISCs like the 486, whatever. This situation will not change, for two reasons. First, MOS will tend to converge on ECL speeds as the transistors continue to get smaller; second, the lower density of ECL will force the ECL implementations to pay off-chip delays to reach functional units that would be on the same chip in an MOS implementation. The significant ECL advantage of low edge rates (relative to frequency) will be addressed by 3.3v MOS parts with carefully designed pad drivers featuring controlled slew rates; designers have learned the lessons of 74F and schottky PALs, and won't repeat those mistakes. -- Jeff Berkowitz N6QOM uunet!sequent!jjb | Bugs are God's way of saying Sequent Computer Systems jjb@sequent.com | you have too much free time.
feustel@netcom.UUCP (David Feustel) (12/30/90)
So when will the 100 Mhz 4(5)86 show up? -- David Feustel, 1930 Curdes Ave, Fort Wayne, IN 46805, (219) 482-9631 EMAIL: netcom.uucp
mslater@cup.portal.com (Michael Z Slater) (12/30/90)
>So when will the 100 Mhz 4(5)86 show up?
The press misinterprets ISSCC papers every year. Intel has NOT announced
a 100 MHz 486. It is simply presenting an ISSCC paper describing such a
chip. This means that it has been able to get one chip to run at this clock
rate with optimal power supply and temperature conditions. It does NOT
mean that it can produce chips to run at this clock rate with usable yield,
or that operate over the fully temperature or power supply range, or that have
bus timing that allows real systems to be built.
As a case in point, Intel previewed the 860 at ISSCC two years ago, and
described it as a 50 MHz part. It was announced at 33 MHz, and about
six months later, a 40 MHz version was shipped. Now, almost two years later,
there is still no 50 MHz 860 in production.
The technology that led to the 100 MHz ISSCC paper is likely to appear in
commercial form as the 50 MHz 486, with 60 to 70 MHz in another year or so.
I don't think you'll see a 100-MHz 486 in the next few years, if ever.
Michael Slater, Microprocessor Report mslater@cup.portal.comsef@kithrup.COM (Sean Eric Fagan) (12/30/90)
In article <37384@cup.portal.com> mslater@cup.portal.com (Michael Z Slater) writes: >The technology that led to the 100 MHz ISSCC paper is likely to appear in >commercial form as the 50 MHz 486, with 60 to 70 MHz in another year or so. >I don't think you'll see a 100-MHz 486 in the next few years, if ever. *sigh* I remember learning that the Cyber 170 had a clock rate of 40MHz, and being impressed by that. Still, I suspect a 40MHz Cyber is going to have higher throughput than a 50Mhz '486. No VM, though, which is a minus. -- Sean Eric Fagan | "I made the universe, but please don't blame me for it; sef@kithrup.COM | I had a bellyache at the time." -----------------+ -- The Turtle (Stephen King, _It_) Any opinions expressed are my own, and generally unpopular with others.