[comp.arch] New SPARC definition, and volatile

peter@ficc.ferranti.com (Peter da Silva) (03/25/91)

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In article <40492@cup.portal.com> mslater@cup.portal.com (Michael Z Slater) writes:
> The version 8 specification adds integer multiply and divide instructions. 
> In addition, a "Store Barrier" instruction was added that requires all stores 
> initiated before it to be completed before operation can continue. This is 
> designed to support future multiprocessor machines that allow memory 
> operations to occur out-of-order.

One thing that occurred to me, reading this, is what impact this sort of
instruction has on the use of "volatile" in C. If "volatile" implies the
use of a "store barrier" instruction on writes, this would impact the
performance of software that's using volatile to (for example) synchronise
lightweight processes on a single CPU, but to not use it would break s/w
that's using spinlocks for multiprocessor synchronisation.

What's the answer? "#pragma really_volatile"?
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