jjb@sequent.UUCP (Jeff Berkowitz) (08/13/89)
In article ... rdh@sli.com (-or- uunet!sli!rdh, Robert D. Houk) writes: > >One of the things I really *HATE* about most "modern" computer systems is >their total black-box'edness. Some don't even have power lights. I really >miss "lights". [this isn't a traditional architecture topic, but "architecture" isn't just ISAs and TLBs and ...] The Sequent machines feature a rectangular array of per-processor activity LEDs on the upper right front of the cabinet. In the Sequent system, there is generally no affinity between jobs and processors; each time a process schedules or an interrupt thread is executed, it is placed on "some available processor". The resulting flickering pattern on the lamps gives them the flavor of an analog display, with the rapid flickering of interactive jobs serving as the background for steady lamps that indicate compute bound processes, etc. The lights can easily be disabled (via a static variable or config file option or something) but to the best of my knowledge no one ever has. When developing drivers in the lab and troubleshooting the inevitable locking and concurrency problems, the ability to see a spinning processor by glancing at the machine is worth a hundred keystrokes in the debugger :-). The developers of a complex parallel application once noticed an odd pattern: all the processor lights on, then all off, pulse, pulse, pulse. After some discussion among their own internals group, a fairly subtle bug in their locking code was found. This would have been very difficult to see with most software analysis tools...with the sampling rate of the aquisition program beating against the bursts of activity in the program. To anyone interested in the system as a whole, they're essential; it's hard to imagine a multiprocessor like the Symmetry without them. Disclaimer: the machine was designed before I came to Sequent; I'm an observer in that sense, and these are my own personal views... -- Jeff Berkowitz N6QOM uunet!sequent!jjb Sequent Computer Systems Custom Systems Group
hull@hpsal2.HP.COM (James Hull) (08/15/89)
> I know something like this exists on the Cray X-MP; do other machines > have cycle counters as well? The HP Precision architecture defines a control register called the Interval Timer for this purpose. Here's the relevant section of the manual: Interval Timer The Interval Timer (CR 16) consists of two internal registers. One of the internal registers is continually counting up by 1 at a rate which is model-dependent and between twice the "peak instruction rate" and half the "peak instruction rate". Reading the Interval Timer returns the value of this internal register. The other internal register contains a comparison value and is set by writing to the Interval Timer. When the counter register and the comparison register contain identical values, bit 0 of the External Interrupt Request Register is set to 1. This causes an external interrupt, if enabled. The Interval Timer can only be written by code running at the most privileged level. If the PSW S-bit is 1, the Interval Timer can only be read by code running at the most privileged level; otherwise, it can be read by code running at any privilege level.
baker@hpfcmgw.HP.COM (Jim Baker) (08/15/89)
> jjb@sequent.UUCP (Jeff Berkowitz) writes: > ... > by glancing at the machine is worth a hundred keystrokes in the debugger :-). I agree. While tuning a relational database on the Sequent Symmetry for the TP1 benchmark, the processor "busy lights" provided invaluable insight to the amount of concurrency being exploited. Jim Baker (ex-Unify employee) Hewlett-Packard
ins_atge@jhunix.HCF.JHU.EDU (Thomas G Edwards) (08/17/89)
The Connection Machine has an LED for every 16 processors... That 512 for each 8K corner cube...A 64K machine must have 4096... The CM looks really neat with its LEDs on. The programmer can (from C/PARIS at least) specify what data in each processor group the LEDs represent. There are also modes which make the LEDs pulse to the system clock, or just stay on continuously. -Thomas Edwards tedwards@cmsun.nrl.navy.mil