[comp.arch] do chip timing specs mean anything

owen@sbcs.sunysb.edu (Owen Kaser) (08/10/90)

Thanks to all those who responded to my posting. I received a few email 
messages in addition.  Their contents were quite interesting, and 
I'm posting selected extracts.  Names of contributors have been omitted, 
in case anonymity is desired. 

-- The original question --
Do timing specs for microprocessors and their support chips bear
any relation to reality, and do industrial designers 
(need to) pay any heed to them? 

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Remember LISP Machine, Inc.?  Well the primary reason the company
failed was because the LAMBDA processor was shipped to customers about
2 years before it was debugged.  One of the many problems was running
the chips over spec.  To compensate for this, there were a few tapped
delay lines that were adjusted at the factory until the machine ran.
Needless to say, the machine was highly temperature sensitive.
....
The people who said that we really didn't need to run within spec were
fired real quick.  ... If the manufacturers
could guarantee that all their chips exceed the specs, they would change
the specs.  If you exceed the specs, you can no longer estimate the
failure rate accurately.

I certainly believe that exceeding the specs is poor engineering
practise. 
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The published timing specs are what the manufacturer *guarantees* as
a minnimum - that is, what is safe enough to get sued about if incorrect.
Such data naturally includes a large margin of safety from what a chip
can really do.
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Statistically speaking, you were very very lucky.  Even though we know our	
components always somewhat exceed our specs, we can't/won't tell you by 
how much and under what conditions.

You will never achieve quality levels measureable in PPM unless you do a 
worst-case design.  Certainly there are many engineers who take easier routes,
but we consider it to be naive and irresponsible.  We NEVER hear about
problems related to our specifications from companies that design their systems
correctly (e.g. HP, Apple, NCR, ...) but we often hear from those who don't.
Something like: "we've been building this for years and we've never had a
problem before" or "we where counting on some margin here".  Sorry, but these
guys don't get a lot of sympathy.

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Yep, its a good idea to pay attention to them.  Depends on the manufacturer.

If you get a part from Intel, their specs are SO BAD that you can bet
the actual parts are gonna be MUCH better.  If you buy a micro from
NSC(Why would you do a silly  thing like that..) you'd find that the
specs tell an accurate story and if you violate them your gonna pay.

 ... Good engineers will design without
violating timing/loading.  This will allow you to margin the design
over power AND temp at the same time.  You SHOULD margin the designs
before you let it out of the lab just to find the last of the flakies.

You'd find that the main-frames are typically the best designs around, i.e.
they will be the most conservative.  They usually aren't done under the
same constraints as designs at start ups, and they have more control
over the parts supply quality.  I've worked at a mainframe manufacturer
as a design engineer....they have "rules" books that tell the designer
which chips they can use, and what the chips performance is.  These numbers
are usually down rated from manufacturer specs(i.e. slower) so they will
have an in-built margin.  Main-frame companies also employ "circuits/package
engineers" that just worry about parts quality, and design quality.  
All the timing violations your boss was so fond of ignoring would be 
disallowed as a valid design at a mainframe company(or any major
company ;-)
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Look at it this way:  Is a manufacturer really going to tell you you can 
only run at x MHz when you can really run at x+1 MHz?  It's not in their 
interests to do so; they want to be able to tell you they've got the 
fastest parts around.

If they're good, they've done their homework and figured out the worst-case
situations for everything.  You may never hit that in a particular design,
for various reasons, but unless you know what their criteria are it's not a
good idea to go outside spec.
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... I always try to live within the
manufacturers worst case specs.  About the only time I ever fudge on
this is when I assume all gates in a single package will exhibit
about the same characteristics, i.e. either they are all close to
the best case or all close to the worst cast.  This seems reasonable
since they are all of the same grade silicon and all at the same
temperature.  Occasionally I run into problems where the worst case
spec of one chip overlaps with the best case (i.e. minimum delay)
of some other chip, such as when timing signals are propagating
through parallel paths.  That is when the above assumption comes
in handy.

...  I've found that most
chips outperform their timing spec, but only at or near room tempera-
ture.  When the box heats up, watch out!

... <discussion of PC clones>... It never ceases to
amaze me how flakey alot of these motherboards can be.  It seems
that a manufacturere will often take a board designed for 16 MHz
and just plug in a 20 or 25MHz crystal.  In fact, I've seen 25 MHz
clock rates with only a 20MHz 80386, and I was told that was common
practice.  However, buying DRAM for these boards is an art.  One
vendor's 80 nsec. DRAM will work while another vendor's will not.
They are obviously so close to the edge that the slight variation
from vendor to vendor upsets the timing. 
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lewine@dg-rtp.dg.com (Donald Lewine) (08/11/90)

In article <1990Aug10.132443.23692@sbcs.sunysb.edu>,
owen@sbcs.sunysb.edu (Owen Kaser) writes:
|> You'd find that the main-frames are typically the best designs
around, i.e.
|> they will be the most conservative.  They usually aren't done under
the
|> same constraints as designs at start ups, and they have more control
|> over the parts supply quality. 

Even more to the point, you can get lucky with a 50 chip design.  It
is harder with a 500 chip design.  With a 5000 chip design, if you 
don't design it worst case it will never work.

I worked on large computers (multiple 30" racks of logic for a CPU)
at a company that also built much smaller systems.  The engineers 
that built the big systems thought that the small system guys did
not do design in enough quality.  The engineers that built the 
small systems thought that the big systems guys took too long in
design and the resulting systems were way too expensive.  Now,
many years later, I see that both design methods were correct for
their respective markets.