gideony@microsoft.UUCP (Gideon Yuvall) (08/17/89)
What is a realistic context-switch penalty for the MIPS, SPARC, 88K, i860 (...) RISC chips? I'm looking for the number of cycles needed to do the task-switch, PLUS the penalty due to the new starting starting out with an "empty" cache. Thanks -- Gideon Yuval, gideony@microsof.UUCP, 206-882-8080 (fax:206-883-8101;TWX:160520)
marc@oahu.cs.ucla.edu (Marc Tremblay) (08/17/89)
In article <7408@microsoft.UUCP> gideony@microsoft.UUCP (Gideon Yuvall) writes: >What is a realistic context-switch penalty for the MIPS, SPARC, >88K, i860 (...) RISC chips? Quoted from IEEE Micro, August 1989: "A typical i860 CPU context switch, including the data cache flush, takes approximately 65 microseconds." For a 40MHz part, 65 microseconds represent 2600 cycles. This includes among other things, invalidating the instruction cache, saving the various on-chip registers, and saving dirty lines of the data cache to main memory (for write-back policy). Marc Tremblay marc@CS.UCLA.EDU