wilson@carcoar.Stanford.EDU (Paul Wilson) (12/18/89)
One of the newsbytes groups (clari.nb.trends) has an article that says the Japanese are claiming to have built a working Josephson computer. They say it's got 26,000 Josephson devices (in 4 chips) on a 10*10 cm board cooled to -268.8 degrees Celsius, and it executes a BILLION (note the B) instructions a second. Consuming 6.2 milliwatts. I'd guess that's for a small in-Josephson-memory program! Hmmm... So I wonder, are we going to switch to bytecoded stack machine uniprocessors? (Or nybblecoded, even?) Locality of reference could be the most important research topic of the next decade. The speed difference between RAM and these CPUs could be like the difference between disks and RAMs. How about centralized cold computer rooms with timeshared barrel processors fed by gigabyte RAIDS (redundant arrays of inexpensive DRAMS :-). Then again, maybe it's cold fusion all over again... even so, it's fun to consider the implications. The return of reference counting? The death of shared memory? Lots of fine-grained optimistic computing to avoid waiting for memory? Any comments on this alleged Japanese breakthrough? Is it true? If so, what does it really mean? Paul R. Wilson Software Systems Laboratory lab ph.: (312) 996-9216 U. of Illin. at C. EECS Dept. (M/C 154) wilson@bert.eecs.uic.edu Box 4348 Chicago,IL 60680 Paul R. Wilson Software Systems Laboratory lab ph.: (312) 996-9216 U. of Illin. at C. EECS Dept. (M/C 154) wilson@carcoar.stanford.edu Box 4348 Chicago,IL 60680
mark@mips.COM (Mark G. Johnson) (12/18/89)
In article <1989Dec18.025843.4435@Neon.Stanford.EDU> wilson@carcoar.Stanford.EDU (Paul Wilson) writes: >One of the newsbytes groups (clari.nb.trends) has an article >that says the Japanese are claiming to have built a working >Josephson computer. > >They say it's got 26,000 Josephson devices (in 4 chips) >on a 10*10 cm board cooled to -268.8 degrees Celsius, >and it executes a BILLION (note the B) instructions >a second. Consuming 6.2 milliwatts. > >I'd guess that's for a small in-Josephson-memory program! If true this is a big step forward in digital JJ's; the previous "record" was a chip that contained 8,454 Josephson interferometers (2,066 gates): Y. Hatano et al, "A 4-bit Josephson Data Processor Chip", IEEE Journal of Solid-State Circuits, Vol. 24 No.5 (Oct 1989) pp. 1312-1316. Note that the researchers chose to build a 4-bit machine. Perhaps the 4 chip, 20K-JJ (~~5K gate?) "computer" mentioned above is indeed a 4-bit CPU plus 512 byte SRAM??? One or two properties of digital JJ circuitry may be of interest here: 1. Every signal wire is a (superconductng) transmission line of rather low impedance, below 5 ohms. So every signal has enough "oomph" to drive off-chip; there is no fan-up penalty for pad drivers. 2. Signals are low-amplitude voltages, on the order of 2.5 millivolts. (See Figures 5, 8 & 10 of the Hatano paper.) They have to be; otherwise driving the low-Z transmission lines would consume excessive power. It is left as an exercise to the reader to interface an F100K ECL SRAM chip (that wants 700mV inputs) with 2.5mV signals from a CPU. 3. Power to the JJ interferometers is supplied via the clocks; there is no DC supply. In Hatano's 4-bit processor, these were 1.02 GHz 100 mV sine waves (and they had to supply 25mW of power). It might be difficult to implement truly asynchronous logic in this family. 4. OR gates, AND gates, and flip-flops were attained by Hatano. Interestingly he doesn't mention inverting gates. OR gates took 9.0 picoseconds, AND gates took 19.4 picoseconds. I don't mean to rain on the JJ parade; merely to suggest that the "computer" alluded to above may not be a 32-bit machine with floating point, virtual memory, and MS-DOS compatibility. :-) -- -- Mark Johnson MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086 (408) 991-0208 mark@mips.com {or ...!decwrl!mips!mark}
mcdonald@aries.scs.uiuc.edu (Doug McDonald) (12/19/89)
In article <33818@mips.mips.COM> mark@mips.COM (Mark G. Johnson) writes: >In article <1989Dec18.025843.4435@Neon.Stanford.EDU> wilson@carcoar.Stanford.EDU (Paul Wilson) writes: > >One of the newsbytes groups (clari.nb.trends) has an article > >that says the Japanese are claiming to have built a working > >Josephson computer. > > > > >I don't mean to rain on the JJ parade; merely to suggest that the "computer" >alluded to above may not be a 32-bit machine with floating point, >virtual memory, and MS-DOS compatibility. :-) >-- That is NOT the point. There is ONLY one point: whatever it is, it is JAPANESE!!! What is the state of the art in AMERICAN JJ computers? Doug McDonald
archer@elysium.esd.sgi.com (Archer Sully) (12/19/89)
In article <1989Dec18.172927.1475@ux1.cso.uiuc.edu>, mcdonald@aries.scs.uiuc.edu (Doug McDonald) writes: > >-- > That is NOT the point. There is ONLY one point: whatever it is, > it is JAPANESE!!! > No, the point is that a researcher working in a laboratory came up with an experimental 4-bit processor. The implications of this are independent of where that researcher was working. So, he was working in Japan, BIG DEAL! This doesn't make his achievement any more or less important. I hope that the discussion will return to the merits of the device, and not dwell on the nationality of the inventor. Archer Sully | A Mind is a Terrible thing to Taste (archer@sgi.com) | - Ministry
mmm@cup.portal.com (Mark Robert Thorson) (12/19/89)
Hmmm... 26,000 devices, that's about 1.5 ENIAC's? I wonder what sort of architecture they used? The most useful things I can think of at that level would be a rasterizing engine and a cryptographic machine.
pcg@aber-cs.UUCP (Piercarlo Grandi) (12/21/89)
In article <25177@cup.portal.com> mmm@cup.portal.com (Mark Robert Thorson) writes: Hmmm... 26,000 devices, that's about 1.5 ENIAC's? I wonder what sort of architecture they used? The most useful things I can think of at that level would be a rasterizing engine and a cryptographic machine. I may be entirely wrong, but the Z8000, which is not a terribly useless processor, and used to run Unix multiuser without trouble at the level of a PDP-11/44 or a VAX 750, was something like 17,000 gates/transistors/devices or whatever (yes, I know that the "whatever" matters), which is in the same ballpark. Anybody knows better? Actually, has anybody thought of the Z8000 as a "RISC"/simple machine (sure the architecture was clean enough), and/or thought doing it in GaAs or other fast, low density technology? In case you have not understood, I liked the Z8000 a lot. If only IBM had chosen it instead of the 8088/8086... If only Zilog had managed to do an MMU and restartable instructions soon enough... -- Piercarlo "Peter" Grandi | ARPA: pcg%cs.aber.ac.uk@nsfnet-relay.ac.uk Dept of CS, UCW Aberystwyth | UUCP: ...!mcvax!ukc!aber-cs!pcg Penglais, Aberystwyth SY23 3BZ, UK | INET: pcg@cs.aber.ac.uk
keith@mips.COM (Keith Garrett) (12/22/89)
In article <1546@aber-cs.UUCP> pcg@cs.aber.ac.uk (Piercarlo Grandi) writes: >In article <25177@cup.portal.com> mmm@cup.portal.com (Mark Robert Thorson) >writes: > > Hmmm... 26,000 devices, that's about 1.5 ENIAC's? I wonder what sort of > architecture they used? The most useful things I can think of at that > level would be a rasterizing engine and a cryptographic machine. > >I may be entirely wrong, but the Z8000, which is not a terribly useless >processor, and used to run Unix multiuser without trouble at the level of a >PDP-11/44 or a VAX 750, was something like 17,000 gates/transistors/devices >or whatever (yes, I know that the "whatever" matters), which is in the same >ballpark. Anybody knows better? my understanding is that the Z8000 contains around 50,000 transistors, which is about 17,000 equivalent logic gates. > >Actually, has anybody thought of the Z8000 as a "RISC"/simple machine (sure >the architecture was clean enough), and/or thought doing it in GaAs or other >fast, low density technology? > >In case you have not understood, I liked the Z8000 a lot. If only IBM had >chosen it instead of the 8088/8086... If only Zilog had managed to do an MMU >and restartable instructions soon enough... the MMU was fairly early, and the virtual memory changes turned out to be relatively easy. the development tools were very late. i think the lack of tools, and a weak marketing effort are what did in the z8000. -- Keith Garrett "This is *MY* opinion, OBVIOUSLY" UUCP: keith@mips.com or {ames,decwrl,prls}!mips!keith USPS: Mips Computer Systems,930 Arques Ave,Sunnyvale,Ca. 94086
jgk@osc.COM (Joe Keane) (12/23/89)
In article <1989Dec18.025843.4435@Neon.Stanford.EDU> wilson@carcoar.Stanford.EDU (Paul Wilson) writes: >So I wonder, are we going to switch to bytecoded stack >machine uniprocessors? (Or nybblecoded, even?) Yes, i think processor word sizes are going to get smaller. No, i don't think we're going to be dealing with uniprocessors. Wait till someone makes a JJ multiprocessor (4 bits of course). That machine will make your head spin. >Locality of reference could be the most important research >topic of the next decade. The speed difference between >RAM and these CPUs could be like the difference between >disks and RAMs. Locality of reference? You're still thinking about an overgrown load/store model. I don't think that's a good way to think about computing. >How about centralized cold computer rooms with timeshared >barrel processors fed by gigabyte RAIDS (redundant >arrays of inexpensive DRAMS :-). Sounds good to me... >Then again, maybe it's cold fusion all over again... >even so, it's fun to consider the implications. The >return of reference counting? The death of shared >memory? Lots of fine-grained optimistic computing >to avoid waiting for memory? Yes, yes, and yes. Seriously. >Any comments on this alleged Japanese breakthrough? Is >it true? If so, what does it really mean? As you pointed out, it shows that global memory access is only going to get more inefficient (relative to CPU). It means that people are going to have to get used to the idea of programming large numbers of fairly simple (but fast) processors.
koopman@a.gp.cs.cmu.edu (Philip Koopman) (12/23/89)
In article <33896@mips.mips.COM>, keith@mips.COM (Keith Garrett) writes: > In article <1546@aber-cs.UUCP> pcg@cs.aber.ac.uk (Piercarlo Grandi) writes: > >In article <25177@cup.portal.com> mmm@cup.portal.com (Mark Robert Thorson) > >writes: > > Hmmm... 26,000 devices, that's about 1.5 ENIAC's? I wonder what sort of > > architecture they used? The most useful things I can think of at that > > level would be a rasterizing engine and a cryptographic machine. > > > >I may be entirely wrong, but the Z8000, which is not a terribly useless > >processor, and used to run Unix multiuser without trouble at the level of a > >PDP-11/44 or a VAX 750, was something like 17,000 gates/transistors/devices 16-bit stack machines (such as the Novix 4000 and RTX 2000) tend to have even fewer gates. The Novix 4000 was so named because it fit on a 4000-gate gate array. And, you don't need more than 16 or so stack elements on-chip to get good speed. Phil Koopman koopman@greyhound.ece.cmu.edu Arpanet 2525A Wexford Run Rd. Wexford, PA 15090 Senior Scientist at Harris Semiconductor. I don't speak for them, and they don't speak for me.
dennisg@kgw2.uucp.WEC.COM (Dennis Glatting) (12/28/89)
In article <1546@aber-cs.UUCP>, pcg@aber-cs.UUCP (Piercarlo Grandi) writes: > > In case you have not understood, I liked the Z8000 a lot. If only IBM had > chosen it instead of the 8088/8086... If only Zilog had managed to do an MMU > and restartable instructions soon enough... > -- why didn't the Z8000 catch on? wasn't it another segmented arch? -- dennisg@kgw2.UUCP.WEC.COM | Dennis P. Glatting ..!uunet!tron!kgw2!dennisg | What! You want that subroutine to produce the same results twice? This is a joke right?