papowell@umn-cs.UUCP (02/28/87)
Thanks to the persons who responded, with a truly overwhelming amount of references. I have merged, pruned, and combined until I think I have the list in a fairly good order. Note that some of the journal articles do not have a Volume or Number reference. The %l entry is intended to be used with Randy Goebels 'refer.e' macro package, which I will post in another article. This package uses the %l field to specify the kind of article. It is FAR superior to the way that refer and bib do things. I find the package invaluable for things. #! /bin/sh # This is a shell archive, meaning: # 1. Remove everything above the #! /bin/sh line. # 2. Save the resulting text in a file. # 3. Execute the file with /bin/sh (not csh) to create: # keyrisc # This archive created: Sat Feb 28 08:46:59 1987 export PATH; PATH=/bin:/usr/bin:$PATH if test -f 'keyrisc' then echo shar: "will not over-write existing file 'keyrisc'" else cat << \SHAR_EOF > 'keyrisc' %T The MODHEL Microcomputer for RISCs Study %l journal-article %A H. Azaria %A D. Tabak %D 1983 %J Microprocessing and Microprogramming %M October-November %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T RIDGE 32 Architecture \(em a RISC Variation %l proceedings-article %A E. Basart %A D. Folger %C Port Chester, New York %D 1983 %J Proceedings Intl. Conference on Computer Design: VLSI in Computers (ICCD 83) %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %M Oct %T RISC Design Streamlines High-Power CPUs %l journal-article %A E. Basart %D 1986 %J Computer Design %M July %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T RISC: Back To The Future? %l journal-article %A C. Bell %D 1986 %J Datamation %M June %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T RISCs -- Reduced Instruction Set Computers -- Make Leap %l journal-article %A R. Bernhard %D 1984 %J Systems and Software %M December %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T More Hardware Means Less Software %l journal-article %A R. Bernhard %D 1986 %J IEEE Spectrum %M December %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T Beyond RISC: High-Precision Architecture %l proceedings-article %A J. Birnbaum %A W. Worley %D 1986 %J Proceedings, Compcon Spring 1986 %M March %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T Understanding Execution Behavior of Software Systems %l journal-article %A J. Browne %D 1984 %J Computer %M July %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T Understanding Execution Behaviour of Software Systems %l journal-article %A J. C. Browne %D 1984 %J Computer %K risc reduced instruction set computer restricted architecture %N 7 %V 17 %T The RISC Factor %l journal-article %A C. Bruno %A S. Brady %D 1986 %J Datamation %M June %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T Building Blocks Yield Fast 32-Bit RISC Machines %l journal-article %A B. Case %D 1985 %J Computer Design %M July %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T u3L: An HLL-RISC Processor for Parallel Execution of FP-Language Programs %l proceedings-article %A M. Castran %A R. P. Organick %D 1982 %J Proc Ninth Annual Symp on Computer Architecture %K RISC %M April %P 239-247 %T Register Allocation and Spilling via Graph Coloring %l proceedings-article %A G. Chaitin %D 1982 %J Proc. SIGPLAN Symp. Compiler Construction %M June %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T Engineering a RISC Compiler System %l proceedings-article %A F. Chow %A M. Himelstein %A E. Killian %A L. Weber %D 1986 %J Proc. COMPCON Spring 1986 %M March %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T Comments on 'The Case for the Reduced Instruction Set Computer' %l journal-article %A D. W. Clark %A W. D. Strecker %D 1980 %J Computer Architecture News %K risc reduced instruction set computer restricted architecture %M October %N 6 %P 34-38 %V 8 %T Fewer Instructions Speed Up VLSI %l journal-article %A B. Clifford %D 1982 %J Electronics %K RISC %M November %N 23 %P 101-102 %V 55 %T Computers, Complexity, and Controversy %l journal-article %A R. Colwell %A C. Hitchcock %A E. Jensen %A L. Weber %D 1985 %J Computer %M September %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T A Perspective on the Processor Complexity Controversy %l proceedings-article %A R. P. Colwell %A C. Y. Hitchcock III %A E. D. Jensen %C Port Chester, New York %D 1983 %J Proceedings Intl. Conference on Computer Design: VLSI in Computers (ICCD 83) %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %M Oct %P 613-616 %T Peering through the RISC/CISC Fog: An Outline of Research %l journal-article %A R. P. Colwell %A C. Y. Hitchcock III %A E. D. Jensen %D 1983 %I ACM %J Computer Architecture News %K archons 432 object-oriented overlapped multiple register sets %M March %N 1 %P 44-50 %V 11 %X attempt to determine if RISCs faster than CISCs, and why %T Compilers for the New Generation of Hewlett-Packard Computers %l proceedings-article %A D. Coutant %A C. Hammond %A J. Kelley %D 1986 %J Proc. COMPCON Spring 1986 %M March %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T A Broader Range of Possible Answers to the Issues Raised by RISC %l proceedings-article %A E. Davidson %D 1986 %J Proc. COMPCON Spring 1986 %M March %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T Operating System Support on a RISC %l proceedings-article %A M. DeMoney %A J. Moore %A J. Mashey %D 1986 %J Proc. COMPCON Spring 1986 %M March %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T Computer Architecture: Some Old Ideas that Haven't Quite Made It Yet %l journal-article %A P. J. Denning %D 1981 %J CACM %K RISC %M September %N 9 %P 553-554 %V 24 %T Altering Computer Architecture is a Way to Raise Throughput Suggests IBM Researchers %l journal-article %A Electronics %D 1976 %J Electronics %K RISC %M December %N 25 %P 30-31 %V 49 %T Very Long Instruction Word Architectures and the ELI 512 %l proceedings-article %A J. A. Fisher %D 1983 %J Int. Symp. on Computer Architecture %K parallel data flow trace scheduling cray-1 RISC multiprocessor %P 140 %T A RISCy Approach to VLSI %l journal-article %A D. T. Fitzpatrick %A J. K. Foderaro %A M. G. H. Katevenis %A H. A. Landman %A D. A. Patterson %A J. B. Peek %A Z. Peshkess %A C. H. Sequin %A R. W. Sherbourne %A K. S. Van Dyke %D 1981 %J VLSI Design %K risc reduced instruction set computer architecture restricted %N 4th Quarter %T Running RISCs %l journal-article %A J. K. Foderaro %A K. S. Van Dyke %A D. A. Patterson %D 1982 %J VLSI Design %K risc reduced instruction set computer architecture restricted %N September/October %T Reduced Instruction Set Multi-Microcomputer System %l proceedings-article %A L. Foti %D 1984 %J Proceedings, National Computer Conference %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T Back-to-Basics Computers with Sports-Car-Speed %l journal-article %A S. Gannes %D 1985 %J Fortune %M Deptember %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T Simple Systems Approach Increases Throughput %l journal-article %A P. Goodrich %D 1985 %J Mini-Micro Systems %M May %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T Floating-Point Arithmetic on a Reduced-Instruction-Set %l proceedings-article %A T. Gross %D 1985 %J Proc., 7th Symp. on Computer Architecture %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T A Perspective on High-Level Language Architecture (extended abstract) %l proceedings-article %A Thomas Gross %A John Hennessy %A Norman Jouppi %A Steven Przybylski %A Christopher Rowen %A Anant Agarwal %A Peter Steenskiste %D 1984 %I Univ. of Maryland %J International Workshop on High-Level Computer Architecture %K risc reduced instruction set computer restricted architecture %M May %T A Performance Evaluation of the Intel iAPX432 %l journal-article %A Hansen %A Mayo %A Linton %A Murphy %A Patterson %D 1982 %J Computer Architecture News %K risc reduced instruction set computer architecture restricted %M June %X bench marks the 432 on the same test programs used to test RISC %T Re-Evaluation of RISC 1 %l journal-article %A J. L. Heath %D 1984 %J Computer Architecture News %K reduced instruction set computer benchmarks 68000 16000 %M March %N 1 %P 3-10 %V 12 %X comparison of performance %T Hardware/Software Tradeoffs for Increased Performance %l manuscript %A J. Hennessy %A N. Jouppi %A F. Baskett %A T. Gross %A J. Gill %J Proc. Symp. on Architectural Supportfor Programming Languages and Operating systems %K risc reduced instruction set computer restricted architecture %O unknown publication %T MIPS: A VLSI Processor Architecture %l book-article %d November 1981 %e G. Steele %i Stanford University Technical Report 223 %p 1-11 %A J. Hennessy %A N. Jouppi %A F. Baskett %A J. Gill %B VLSI Systems and Computations %D 1981 %E H. T. Kung %E R. Sproull %I Computer Science Press %K MIPS, RISC, pipelines delayed branch jump reduced instruction set computer, %P 337-346 %X MIPS is a new single chip VLSI processor architecture. It attempts to achieve high performance with the use of a simplified instruction set, similar to those found in microengines. The processor is a fast pipelined engine without pipeline interlocks. %T MIPS: A VLSI Processor Architecture %l proceedings-article %A J. Hennessy %A et al %D 1981 %J Proc of the CMU Conference on VLSI systems And Computations %K RISC %M October %P 337-346 %T MIPS: A VLSI Processor Architecture %l book-article %e G. Steele %A J. Hennessy %A N. Jouppi %A F. Baskett %A J. Gill %B VLSI Systems and Computations %D 1981 %E H. T. Kung %E R. Sproull %I Computer Science Press %K pipelines delayed branch jump reduced instruction set computer risc %P 337-346 %T MIPS: A VLSI Processor Architecture %l proceedings-article %A J. Hennessy %A et al %D 1981 %J Proc of the CMU Conference on VLSI systems And Computations %K RISC %M October %P 337-346 %T The MIPS Machine %l proceedings-article %A J. Hennessy %A et al %D 1982 %J Proceedings of COMPCON Spring 82 %K RISC %M February %P 2-7 %T MIPS: A Microprocessor Architecture %l proceedings-article %A J. Hennessy %A N. Jouppi %A S. Przybylski %A C. Rowen %A T. Gross %A F. Baskett %A J. Gill %D 1982 %J 15th Ann. Workshop on Microprogramming %K risc reduced instruction set computer architecture restricted %M November %P 17-22 %X related paper in VLSI Systems and Computations %T The MIPS Machine %l proceedings-article %A J. Hennessy %A et al %D 1982 %J Proceedings of COMPCON Spring 82 %K RISC %M February %P 2-7 %T MIPS: A Microprocessor Architecture %l proceedings-article %A J. Hennessy %A N. Jouppi %A S. Przybylski %A C. Rowen %A T. Gross %A F. Baskett %A J. Gill %D 1982 %J 15th Ann. Workshop on Microprogramming %K risc reduced instruction set computer architecture restricted %M November %P 17-22 %T Performance Issues in VLSI Processor Design %l proceedings-article %A J. Hennessy %A N. Jouppi %A S. Przybylski %A C. Rowen %A T. Gross %D 1983 %J Proc. Intl. Conf. on Computer Design (ICCD) %K mips risc reduced restricted instruction set computer architecture ---- pipelining microcoding %P 153-156 %T Postpass Code Optimization of Pipeline Constraints %l journal-article %A J. Hennessy %A T. Gross %D 1983 %J ACM Transactions on Programming Languages and Systems %M July %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T Performance Issues in VLSI Processor Design %l proceedings-article %A J. Hennessy %A N. Jouppi %A S. Przybylski %A C. Rowen %A T. Gross %C Port Chester, New York %D 1983 %J Proceedings Intl. Conference on Computer Design: VLSI in Computers (ICCD 83) %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %M Oct %P 153-156 %T VLSI Processor Architecture %l journal-article %A J. Hennessy %D 1984 %J IEEE Transactions on Computers %M December %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T SPUR: A VLSI Multiprocessor Workstation %l technical-report %a et al %A M.D. Hill %A S. J. Eggers %A J. R. Larus %A D. A. Hodges %A R. H. Katz %A J. Ousterhout %A D. A. Patterson %C Berkeley %D 1985 %I Computer Science Division, University of California %K address translation, cache, cache consistency, IEEE floating-point, Lisp, multiprocessor, RISC, shared-bus, tagged architecture %M December %P 27 %R UCB/CSD 86/273 %X SPUR (Symbolic Processing Using RISCs) is a workstation for conducting parallel processing research. SPUR conatins 6 to 12 high-performance homogenous processors connected with a shared bus. The number of processors is large enough to permit parallel processing experiments, but small enough to allow packaging as a personal workstation. %T IBM RISC Workstation Features 40-Bit Virtual Addressing %l journal-article %A H. Hinden %D 1986 %J Computer Design %M February %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T Analyzing Multiple Register Sets %l journal-article %A C. Hitchcock %A H. Brinkley %D 1985 %J 12th Symp. on Computer Architecture %M June %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T A Definition of RISC %l proceedings-article %A Martin E. Hopkins %D 1984 %I Univ. of Maryland %J International Workshop on High-Level Computer Architecture %K risc reduced instruction set computer restricted architecture %M May %P 8-11 %X Tries to definite RISCs in the IBM 801 context in comparison to the IBM 370 %T HLLDA Defies RISC: Thoughts on RISCs, CISCs, and HLLDAs %l journal-article %A W. Hopkins %D 1983 %J 16th Symp. on Microprogramming %M December %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T HLLDA Defies RISC: Thoughts on RISCs, CISCs, and HLLDAs %l proceedings-article %A W. C. Hopkins %C Downingtown, Pa. %J MICRO 16, Proc. 16th Annual Microprogramming Workshop %M Oct %Y 1983 %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T The RISC II Micro-Architecture %l journal-article %A M. G. H Katevenis %A R. W. Sherburne %A D. A. Patterson %A C. H. Sequin %D 1983 %J VLSI 83 %K risc reduced instruction set computer architecture restricted %M August %T Reduced Instruction Set Computer Architectures for VLSI %l dissertation %A Manolis G. H. Katevenis %C Berkeley, CA 94720 %D 1983 %I University of California %K risc reduced instruction set computer architecture %R UCB/CSD 83/141 %S Computer Science Division %X This is the Ph. D. thesis written by one of the designers of the RISC I & II. There is a nice summary of the RISC project, the rationale behind it, and implementation details of the RISC II chip. Subsequently published by the ACM. %T Memory Hierarchy Aspects of a Multiprocessor RISC: Cache and Bus Analyses %l technical-report %A R. H. Katz %A S. J. Eggers %A G. A. Gibson %A P. M. Hansen %A M. D. Hill %A J. M. Pendleton %A S. A. Ritchie %A G. S. Taylor %A D. A. Wood %A D. A. Patterson %D 1985 %I Computer Science Division (EECS), University of California, Berkeley %K RISC Architecture, Tightly Compled Multiprocessor, Memory Hierarchy, Cache Design %M January %R UCB/CSD 85/221 %Y UCB85 %X We describe the memory system design of a tightly-coupled multiprocessor. Each processor node consists of a VLSI RISC processor, a VLSI cache controller, cache data RAMS, and a standard bus. We show that adequate performance can be achieved only if the processor has an on-chip instruction buffer and a large %T Are RISCs Subsets of CISCs? %l journal-article %A E. Korthaver %A L. Richter %D 1984 %J Microprocessing and Microprogramming %M August %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T A Comparison of Microcode, Assembly Code, and High-Level Languages on the VAX-11 and RISC I %l journal-article %A J. R. Larus %D 1982 %J Computer Architecture News %K risc reduced instruction set computer architecture restricted %M September %N 5 %P 10-15 %V 10 %T A Small, High-speed Dataflow Processor %l proceedings-article %A W. Leler %A H. J. Siegel %A L. Siegel %C Bellarire, MI. %D 1983 %J Proc. 1983 Conf. on Parallel Processing %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %M Aug %T An Algorithm to Compact a VLSI Symbolic Layout with Mixed Constraints %l journal-article %A Yuh-Zen Liao %A C. K. Wong %D 1983 %J IEEE Trans. on Computer Aided Design %K risc reduced instruction set computer restricted architecture %M April %N 2 %V CAD-2 %T Empirical Evaluation of Some Features of Instruction Set Processor Architectures %l journal-article %A A. Lunde %D 1972 %J CACM %M March %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T Instruction-Level Program and Processor Modeling %l journal-article %A M. MacDougall %D 1984 %J Computer %M July %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T RISC Chips %l journal-article %A J. Markoff %D 1984 %J Byte %K RISC %M November %N 11 %P 191-206 %V 9 %T IBM Mini a Radical Departure %l journal-article %A V. McLellan %D 1979 %J Datamation %K RISC %M October %N 11 %P 53-55 %V 25 %T Simplicity is Focus in Efforts to Increase Computer Power %l journal-article %A M. Miller %D 1985 %J Wall Street Journal %M August %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T Gambling on RISC %l journal-article %A J. Moad %D 1986 %J Datamation %M June %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T New RISC Machines Appear as Hybrids with Both RISC and CISC Features %l journal-article %A N. Mokhoff %D 1986 %J Computer Design %M April %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T A CMOS RISC Processor with Integrated Systems Functions %l proceedings-article %A J. Moussoris %D 1986 %J Proc. COMPCON Spring 1986 %M March %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T C Compiler Implementation Issues on the Clipper %l proceedings-article %A D. Neff %D 1986 %J Proc. COMPCON Spring 1986 %M March %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T Clipper Microprocessor Architecture Overview %l proceedings-article %A L. Neff %D 1986 %J Proc. COMPCON Spring 1986 %M March %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T Internal Floating-point Processor Further Boosts RISC Machine Speed %l journal-article %A S. Ohr %D 1984 %J Electronics Design %K risc reduced instruction set computer restricted architecture %N 18 %V 32 %T RISC Machines %l journal-article %A S. Ohr %D 1985 %J Electronic Design %M January %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T Tradeoffs in the design of a system for high level language interpretation %l proceedings-article %A F. C. C. Osorio %A Y. N. Patt %D 1983 %J Proc. Intl. Conf. on Computer Design (ICCD) %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %M Oct %T Assessing RISCs in High Level Language Support %l journal-article %A D. Patterson %A R. Piepho %D 1982 %J IEEE Micro %M November %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T Architecture of a VLSI Instruction Cache for a RISC %l proceedings-article %A D. Patterson %D 1983 %J Proc. 10th Computer Architecture Conference %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T Reduced Instruction Set Computers %l journal-article %A D. Patterson %D 1985 %J CACM %M January %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T The Case for the Reduced Instruction Set Computer %l journal-article %A D. A. Patterson %A D. R. Ditzel %D 1980 %J Computer Architecture News %K risc reduced instruction set computer restricted architecture %M October %N 6 %V 8 %T RISC 1: A Reduced Instruction Set VLSI Computer %l proceedings-article %A D. A. Patterson %A C. H. Sequin %D 1981 %J 8th. Ann. Symp. on Computer Architecture %K risc reduced instruction set computer restricted architecture %M May %P 443-457 %T RISC Assessment: A High-Level Language Experiment %l proceedings-article %A D. A. Patterson %A R. S. Piepho %D 1982 %J 9th Symp. on Computer Architecture %K risc reduced instruction set computer architecture restricted %M April %P 3-8 %T A VLSI RISC %l journal-article %A D. A. Patterson %A C. H. Sequin %D 1982 %I IEEE %J Computer %K risc reduced instruction set computer architecture restricted %M September %N 9 %P 8-21 %V 15 %T RISC Assessment: A High-Level Language Experiment %l proceedings-article %A D. A. Patterson %A R. S. Piepho %D 1982 %J 9th Symp. on Computer Architecture %K risc reduced instruction set computer architecture restricted %M April %P 3-8 %T A VLSI RISC %l journal-article %A D. A. Patterson %A C. H. Sequin %D 1982 %J Computer %K risc reduced instruction set computer architecture restricted %M September %N 9 %P 8-21 %V 15 %T A RISCy APPROACH TO COMPUTER DESIGN %l proceedings-article %A D. A. Patterson %D 1982 %I IEEE Computer Society press %J COMPCON %K risc reduced instruction set computer architecture restricted %M Spring %P 8-14 %T Architecture of a VLSI Instruction Cache for a RISC %l proceedings-article %A D. A. Patterson %A P. Garrison %A M. Hill %A D. Lioupis %A C. Nyberg %A T. Sippel %A K. Van Dyke %D 1983 %J Int. Symp. on Computer Architecture %K fault tolerance associative memory SAMOS remote program counter jump branch likely bit %P 108 %T RISC Watch %l journal-article %A D. A. Patterson %D 1984 %J Computer Architecture News %K reduced instruction set computer benchmarks %M March %N 1 %P 11-19 %V 12 %T A RISCy APPROACH TO COMPUTER DESIGN %l proceedings-article %A David A. Patterson %D 1982 %I IEEE Computer Society press %J Digest of papers, Spring COMPCON 82 %K risc reduced instruction set computer architecture restricted %M Spring %P 8-14 %T The 801 Minicomputer %l proceedings-article %A G. Radin %D 1982 %J Proceedings from the Symposium on Architectural Support for Programming Languages and Operating Systems %M March %P 39-47 %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T The 801 Minicomputer %l journal-article %A G. Radin %D 1983 %J IBM J. Res. Dev. %K RISC computer architecture IBM 801 cache %N 3 %P 237 %V 27 %T Applying RISC Theory to a Large Computer %l journal-article %A R. Ragan-Kelley %A R. Clark %D 1983 %J Computer Design %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %M November %N 13 %P 191-198 %V 22 %T A Reduced High-Level-Language Instruction Set %l journal-article %A P. U. Schultess %D 1984 %J Micro %K descriptor based addressing stack architecture reduced instruction set computer risc language directed %M June %N 3 %P 55-67 %V 4 %T OPA - A New Architecture for Pascal-Like Languages %l journal-article %A P. Schulthess %A F. Vonaesch %D 1982 %J ACM Computer Architecture News %K stack RISC language directed %M Dec %N 6 %P 9 %V 10 %T Pyramid Challenges DEC with RISC Supermini %l journal-article %A M. Seither %D 1985 %J Mini-Micro Systems %M August %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T Design and Implementation of RISC I %l book-article %A C. H. Sequin %A D. A. Patterson %K computer architecture register testing %P 276-298 %T MIPS, Dhrystones, and Other Tales %l journal-article %A O. Serlin %D 1986 %J Datamation %M June %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T Local Memory In RISCs %l proceedings-article %A R. W. Sherburne %A M. Katenvenis %A D. A. Patterson %A C. H. Sequin %C Port Chester, New York %D 1983 %J Proceedings Intl. Conference on Computer Design: VLSI in Computers (ICCD 83) %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %M Oct %T The RISC II Micro-architecture %l proceedings-article %A R. W. Sherburne %A M. Katenvenis %A D. A. Patterson %A C. H. Sequin %D 1983 %J Proc. Intl. Conf. on Computer Design (ICCD) %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %M Oct %T MOVE Architecture in Digital Computers %l journal-article %A Daniel Tabak %A G. J. Lipovski %D 1980 %J IEEE Trans. on Computers %K RISC CMOVE architecture %M February %N 2 %P 180-189 %V C-29 %T Strategies for Managing the Register File in RISC %l journal-article %A Y. Tamir %A C. H. Sequin %D 1983 %J IEEE Trans. on Computers %K risc reduced instruction set computer restricted architecture %M Nov %T Implications of Structured Programming for Machine Architecture %l journal-article %A A. Tanenbaum %D 1978 %J CACM %M March %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T VLSI Processor Architectures %l journal-article %A P. Treleaven %D 1982 %J Computer %M June %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T Architecture of SOAR: Smalltalk on a Risc %l proceedings-article %A D. Ungar %A R. Blau %A P. Foley %A D. Samples %A D. Patterson %D 1984 %I SIGARCH %J 11th Annual International Symposium on Computer Architecture %K object oriented architectures reduced instruction set architectures tagged object oriented architectures garbage collection %P 188-197 %T Toward Simpler, Faster Computers %l journal-article %A P. Wallich %D 1985 %J IEEE Spectrum %M August %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T IBM RT Personal Computer Technology %l technical-report %A F. Waters, ed. %D 1986 %I IBM %R SA23-1057 %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %T A Language-Oriented Approach for Implementing Branches: Structured Control Flow %l proceedings-article %A Robert G. Wedig %D 1984 %I Univ. of Maryland %J International Workshop on High-Level Computer Architecture %K risc reduced instruction set computer restricted architecture %M May %P 3.1-3.7 %T Keeping Jump Instructions out of the Pipeline of a RISC-Like Computer %l journal-article %A M. V. Wilkes %D 1983 %I ACM %J Computer Architecture News %M Dec %N 5 %P 5-7 %V 11 %K mips risc reduced restricted instruction set computer architecture pipelining microcoding %K mips risc reduced restricted instruction set computer architecture pipelining microcoding SHAR_EOF fi exit 0 # End of shell archive -- Patrick Powell, Dept. Computer Science, 136 Lind Hall, 207 Church St. SE, University of Minnesota, Minneapolis, MN 55455 (612)625-3543/625-4002